mmu/fsm: test case for mtspr

[soc.git] / src / soc / fu / common_input_stage.py

diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py
index 745be7726b032fa29b6d4cbbfe45c2140c90e0b7..e36b14db340905cdf097cd084f1f3e9a0a6ca007 100644 (file)
--- a/src/soc/fu/common_input_stage.py
+++ b/src/soc/fu/common_input_stage.py
@@ -19,8 +19,12 @@ class CommonInputStage(PipeModBase):
         # operand a to be as-is or inverted
         a = Signal.like(self.i.a)
 
-        if hasattr(op, "invert_a"):
-            with m.If(op.invert_a):
+        op_to_invert = 'ra'
+        if hasattr(self, "invert_op"):
+            op_to_invert = self.invert_op
+
+        if hasattr(op, "invert_in") and op_to_invert == 'ra':
+            with m.If(op.invert_in):
                 comb += a.eq(~self.i.a)
             with m.Else():
                 comb += a.eq(self.i.a)
@@ -29,6 +33,21 @@ class CommonInputStage(PipeModBase):
 
         comb += self.o.a.eq(a)
 
+        ##### operand B #####
+
+        # operand b to be as-is or inverted
+        b = Signal.like(self.i.b)
+
+        if hasattr(op, "invert_in") and op_to_invert == 'rb':
+            with m.If(op.invert_in):
+                comb += b.eq(~self.i.b)
+            with m.Else():
+                comb += b.eq(self.i.b)
+        else:
+            comb += b.eq(self.i.b)
+
+        comb += self.o.b.eq(b)
+
         ##### carry-in #####
 
         # either copy incoming carry or set to 1/0 as defined by op
@@ -47,8 +66,7 @@ class CommonInputStage(PipeModBase):
         ##### sticky overflow and context (both pass-through) #####
 
         if hasattr(self.o, "xer_so"): # hack (for now - for LogicalInputData)
-            with m.If(op.oe.oe_ok):
-                comb += self.o.xer_so.eq(self.i.xer_so)
+            comb += self.o.xer_so.eq(self.i.xer_so)
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m