mmu/fsm: test case for mtspr

[soc.git] / src / soc / fu / common_input_stage.py

diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py
index cd1620964e333bf8e5d793edf5b0c28b766a0052..e36b14db340905cdf097cd084f1f3e9a0a6ca007 100644 (file)
--- a/src/soc/fu/common_input_stage.py
+++ b/src/soc/fu/common_input_stage.py
@@ -3,7 +3,7 @@
 # generation for subtraction, should happen here
 from nmigen import (Module, Signal)
 from nmutil.pipemodbase import PipeModBase
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
 from soc.decoder.power_enums import CryIn
 
 
@@ -19,8 +19,12 @@ class CommonInputStage(PipeModBase):
         # operand a to be as-is or inverted
         a = Signal.like(self.i.a)
 
-        if hasattr(op, "invert_a"):
-            with m.If(op.invert_a):
+        op_to_invert = 'ra'
+        if hasattr(self, "invert_op"):
+            op_to_invert = self.invert_op
+
+        if hasattr(op, "invert_in") and op_to_invert == 'ra':
+            with m.If(op.invert_in):
                 comb += a.eq(~self.i.a)
             with m.Else():
                 comb += a.eq(self.i.a)
@@ -29,6 +33,21 @@ class CommonInputStage(PipeModBase):
 
         comb += self.o.a.eq(a)
 
+        ##### operand B #####
+
+        # operand b to be as-is or inverted
+        b = Signal.like(self.i.b)
+
+        if hasattr(op, "invert_in") and op_to_invert == 'rb':
+            with m.If(op.invert_in):
+                comb += b.eq(~self.i.b)
+            with m.Else():
+                comb += b.eq(self.i.b)
+        else:
+            comb += b.eq(self.i.b)
+
+        comb += self.o.b.eq(b)
+
         ##### carry-in #####
 
         # either copy incoming carry or set to 1/0 as defined by op
@@ -40,6 +59,9 @@ class CommonInputStage(PipeModBase):
                     comb += self.o.xer_ca.eq(0b11) # XER CA/CA32
                 with m.Case(CryIn.CA):
                     comb += self.o.xer_ca.eq(self.i.xer_ca)
+                # XXX TODO
+                #with m.Case(CryIn.OV):
+                #    comb += self.o.xer_ca.eq(self.i.xer_ov)
 
         ##### sticky overflow and context (both pass-through) #####