test top bit 31 in 32-bit mode for CR0 creation

[soc.git] / src / soc / fu / common_output_stage.py

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index 5d5f0cb4f5382a816fcd7344e35508c0c8bbdae1..fb1310cad2c4ed92381d0bb64ea002673590387a 100644 (file)
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -55,7 +55,10 @@ class CommonOutputStage(PipeModBase):
 
         comb += is_cmp.eq(op.insn_type == InternalOp.OP_CMP)
         comb += is_cmpeqb.eq(op.insn_type == InternalOp.OP_CMPEQB)
-        comb += msb_test.eq(target[-1] ^ is_cmp)
+        with m.If(op.is_32bit):
+            comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB
+        with m.Else():
+            comb += msb_test.eq(target[31] ^ is_cmp) # 32-bit MSB
         comb += is_nzero.eq(target.bool())
         comb += is_positive.eq(is_nzero & ~msb_test)
         comb += is_negative.eq(is_nzero & msb_test)