# and updating the condition register
from nmigen import (Module, Signal, Cat, Const)
from nmutil.pipemodbase import PipeModBase
-from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import MicrOp
+from ieee754.part.partsig import SimdSignal
+from openpower.decoder.power_enums import MicrOp
class CommonOutputStage(PipeModBase):
xer_so_o = self.o.xer_so.data[0]
so = Signal(reset_less=True)
oe = Signal(reset_less=True)
- comb += oe.eq(op.oe.oe & op.oe.oe_ok)
+ comb += oe.eq(op.oe.oe & op.oe.ok)
with m.If(oe):
comb += so.eq(xer_so_o)
with m.Else():
else:
so = xer_so_i
- # op requests inversion of the output...
- o = Signal.like(self.i.o)
- if hasattr(op, "invert_out"): # ... optionally
- with m.If(op.invert_out):
- comb += o.eq(~self.i.o.data)
- with m.Else():
- comb += o.eq(self.i.o.data)
- else:
- comb += o.eq(self.i.o.data) # ... no inversion
+ with m.If(~op.sv_pred_dz): # when SVP64 zeroing is set, output is zero
+ # op requests inversion of the output...
+ o = Signal.like(self.i.o)
+ if hasattr(op, "invert_out"): # ... optionally
+ with m.If(op.invert_out):
+ comb += o.eq(~self.i.o.data)
+ with m.Else():
+ comb += o.eq(self.i.o.data)
+ else:
+ comb += o.eq(self.i.o.data) # ... no inversion
# target register if 32-bit is only the 32 LSBs
# XXX ah. right. this needs to be done only if the *mode* is 32-bit
+ # (an MSR bit)
# see https://bugs.libre-soc.org/show_bug.cgi?id=424
target = Signal(64, reset_less=True)
#with m.If(op.is_32bit):
comb += is_cmp.eq(op.insn_type == MicrOp.OP_CMP)
comb += is_cmpeqb.eq(op.insn_type == MicrOp.OP_CMPEQB)
- # nope - if *processor* mode is 32-bit
- #with m.If(op.is_32bit):
- # comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB
- #with m.Else():
- # comb += msb_test.eq(target[31] ^ is_cmp) # 32-bit MSB
- comb += msb_test.eq(target[-1]) # 64-bit MSB
+
+ comb += msb_test.eq(target[-1]) # 64-bit MSB, TODO 32-bit MSB
comb += is_nzero.eq(target.bool())
- with m.If(is_cmp): # invert pos/neg tests
- comb += is_positive.eq(msb_test)
- comb += is_negative.eq(is_nzero & ~msb_test)
- with m.Else():
- comb += is_negative.eq(msb_test)
- comb += is_positive.eq(is_nzero & ~msb_test)
+ comb += is_negative.eq(msb_test)
+ comb += is_positive.eq(is_nzero & ~msb_test)
- with m.If(is_cmpeqb):
+ with m.If(is_cmpeqb | is_cmp):
comb += cr0.eq(self.i.cr0.data)
with m.Else():
comb += cr0.eq(Cat(so, ~is_nzero, is_positive, is_negative))
# copy out [inverted?] output, cr0, and context out
comb += self.o.o.data.eq(o)
comb += self.o.o.ok.eq(self.i.o.ok)
- # CR0 to be set
- comb += self.o.cr0.data.eq(cr0)
+ comb += self.o.cr0.data.eq(cr0) # CR0 to be set
comb += self.o.cr0.ok.eq(op.write_cr0)
- # context
- comb += self.o.ctx.eq(self.i.ctx)
+ comb += self.o.ctx.eq(self.i.ctx) # context
return m