# This stage is intended to handle the gating of carry out,
# and updating the condition register
-from nmigen import (Module, Signal, Cat)
+from nmigen import (Module, Signal, Cat, Const)
from nmutil.pipemodbase import PipeModBase
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
class CommonOutputStage(PipeModBase):
m = Module()
comb = m.d.comb
op = self.i.ctx.op
+ if hasattr(self.o, "xer_so"):
+ xer_so_o = self.o.xer_so.data[0]
+ else:
+ xer_so_o = Const(0, 1)
# op requests inversion of the output...
o = Signal.like(self.i.o)
# that can be used as a test of whether to invert the +ve/-ve test
# see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
- comb += is_cmp.eq(op.insn_type == InternalOp.OP_CMP)
- comb += is_cmpeqb.eq(op.insn_type == InternalOp.OP_CMPEQB)
+ comb += is_cmp.eq(op.insn_type == MicrOp.OP_CMP)
+ comb += is_cmpeqb.eq(op.insn_type == MicrOp.OP_CMPEQB)
# nope - if *processor* mode is 32-bit
#with m.If(op.is_32bit):
# comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB
with m.If(is_cmpeqb):
comb += cr0.eq(self.i.cr0.data)
with m.Else():
- comb += cr0.eq(Cat(self.so, ~is_nzero, is_positive, is_negative))
+ comb += cr0.eq(Cat(xer_so_o, ~is_nzero, is_positive, is_negative))
# copy out [inverted?] output, cr0, and context out
comb += self.o.o.data.eq(o)