more updating spr1/spr2 to fast1/fast2

[soc.git] / src / soc / fu / compunits / compunits.py

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index c8e4a2bcafcc834aa403177a2a70c5daed7c6c01..6de63d059dff17e07058c0493547af6897212448 100644 (file)
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -45,6 +45,7 @@ see:
 from nmigen import Elaboratable, Module
 from nmigen.cli import rtlil
 from soc.experiment.compalu_multi import MultiCompUnit
+from soc.decoder.power_enums import Function
 
 # pipeline / spec imports
 
@@ -63,6 +64,15 @@ from soc.fu.branch.pipe_data import BranchPipeSpec
 from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
 from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec
 
+from soc.fu.trap.pipeline import TrapBasePipe
+from soc.fu.trap.pipe_data import TrapPipeSpec
+
+from soc.fu.div.pipeline import DIVBasePipe
+from soc.fu.div.pipe_data import DIVPipeSpec
+
+from soc.fu.ldst.pipe_data import LDSTPipeSpec
+from soc.experiment.compldst_multi import LDSTCompUnit # special-case
+
 
 ###################################################################
 ###### FunctionUnitBaseSingle - use to make single-stge pipes #####
@@ -86,12 +96,13 @@ class FunctionUnitBaseSingle(MultiCompUnit):
     decoding) which read-register ports are to be requested.  this is not
     ideal (it could be a lot neater) but works for now.
     """
-    def __init__(self, speckls, pipekls):
+    def __init__(self, speckls, pipekls, idx):
+        alu_name = "alu_%s%d" % (self.fnunit.name.lower(), idx)
         pspec = speckls(id_wid=2)                # spec (NNNPipeSpec instance)
         opsubset = pspec.opsubsetkls             # get the operand subset class
         regspec = pspec.regspec                  # get the regspec
         alu = pipekls(pspec)                     # create actual NNNBasePipe
-        super().__init__(regspec, alu, opsubset) # pass to MultiCompUnit
+        super().__init__(regspec, alu, opsubset, name=alu_name) # MultiCompUnit
 
 
 ##############################################################
@@ -105,19 +116,48 @@ class FunctionUnitBaseMulti:
 ###### actual Function Units: these are "single" stage pipelines #####
 
 class ALUFunctionUnit(FunctionUnitBaseSingle):
-    def __init__(self): super().__init__(ALUPipeSpec, ALUBasePipe)
+    fnunit = Function.ALU
+    def __init__(self, idx):
+        super().__init__(ALUPipeSpec, ALUBasePipe, idx)
 
 class LogicalFunctionUnit(FunctionUnitBaseSingle):
-    def __init__(self): super().__init__(LogicalPipeSpec, LogicalBasePipe)
+    fnunit = Function.LOGICAL
+    def __init__(self, idx):
+        super().__init__(LogicalPipeSpec, LogicalBasePipe, idx)
 
 class CRFunctionUnit(FunctionUnitBaseSingle):
-    def __init__(self): super().__init__(CRPipeSpec, CRBasePipe)
+    fnunit = Function.CR
+    def __init__(self, idx):
+        super().__init__(CRPipeSpec, CRBasePipe, idx)
 
 class BranchFunctionUnit(FunctionUnitBaseSingle):
-    def __init__(self): super().__init__(BranchPipeSpec, BranchBasePipe)
+    fnunit = Function.BRANCH
+    def __init__(self, idx):
+        super().__init__(BranchPipeSpec, BranchBasePipe, idx)
 
 class ShiftRotFunctionUnit(FunctionUnitBaseSingle):
-    def __init__(self): super().__init__(ShiftRotPipeSpec, ShiftRotBasePipe)
+    fnunit = Function.SHIFT_ROT
+    def __init__(self, idx):
+        super().__init__(ShiftRotPipeSpec, ShiftRotBasePipe, idx)
+
+class DIVFunctionUnit(FunctionUnitBaseSingle):
+    fnunit = Function.DIV
+    def __init__(self, idx):
+        super().__init__(DIVPipeSpec, DIVBasePipe, idx)
+
+class TrapFunctionUnit(FunctionUnitBaseSingle):
+    fnunit = Function.TRAP
+    def __init__(self, idx):
+        super().__init__(TrapPipeSpec, TrapBasePipe, idx)
+
+# special-case
+class LDSTFunctionUnit(LDSTCompUnit):
+    fnunit = Function.LDST
+    def __init__(self, pi, awid, idx):
+        pspec = LDSTPipeSpec(id_wid=2)           # spec (NNNPipeSpec instance)
+        opsubset = pspec.opsubsetkls             # get the operand subset class
+        regspec = pspec.regspec                  # get the regspec
+        super().__init__(pi, regspec, awid, opsubset)
 
 
 #####################################################################
@@ -128,15 +168,39 @@ class ShiftRotFunctionUnit(FunctionUnitBaseSingle):
 
 # simple one-only function unit class, for test purposes
 class AllFunctionUnits(Elaboratable):
-    def __init__(self):
+    """AllFunctionUnits
+
+    creates a dictionary of Function Units according to required spec.
+    tuple is of:
+
+     * name of ALU,
+     * quantity of FUs required
+     * type of FU required
+
+    """
+    def __init__(self, pspec, pilist=None):
+        addrwid = pspec.addr_wid
+        units = pspec.units
+        if not isinstance(units, dict):
+            units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
+                     'div': 1, 'shiftrot': 1}
+        alus = {'alu': ALUFunctionUnit,
+                 'cr': CRFunctionUnit,
+                 'branch': BranchFunctionUnit,
+                 'trap': TrapFunctionUnit,
+                 'div': DIVFunctionUnit,
+                 'logical': LogicalFunctionUnit,
+                 'shiftrot': ShiftRotFunctionUnit,
+                }
         self.fus = {}
-        for (name, qty, kls) in (('alu', 1, ALUFunctionUnit),
-                            ('cr', 1, CRFunctionUnit),
-                            ('branch', 1, BranchFunctionUnit),
-                            ('logical', 1, LogicalFunctionUnit),
-                            ('shiftrot', 1, ShiftRotFunctionUnit)):
+        for name, qty in units.items():
+            kls = alus[name]
             for i in range(qty):
-                self.fus["%s%d" % (name, i)] = kls()
+                self.fus["%s%d" % (name, i)] = kls(i)
+        if pilist is None:
+            return
+        for i, pi in enumerate(pilist):
+            self.fus["ldst%d" % (i)] = LDSTFunctionUnit(pi, addrwid, i)
 
     def elaborate(self, platform):
         m = Module()
@@ -156,9 +220,10 @@ def tst_single_fus_il():
     for (name, kls) in (('alu', ALUFunctionUnit),
                         ('cr', CRFunctionUnit),
                         ('branch', BranchFunctionUnit),
+                        ('trap', TrapFunctionUnit),
                         ('logical', LogicalFunctionUnit),
                         ('shiftrot', ShiftRotFunctionUnit)):
-        fu = kls()
+        fu = kls(0)
         vl = rtlil.convert(fu, ports=fu.ports())
         with open("fu_%s.il" % name, "w") as f:
             f.write(vl)