add bigendian flag

[soc.git] / src / soc / fu / compunits / test / test_alu_compunit.py

diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index 6041cd3ec2ab185bfd7ac1eb83b99e020786b3d8..001f73922324c4cace171962646ac985b4443576 100644 (file)
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -1,56 +1,32 @@
 import unittest
-from soc.decoder.power_enums import (XER_bits,)
+from soc.decoder.power_enums import (XER_bits, Function)
 
-from soc.fu.alu.test.test_pipe_caller import TestCase, ALUTestCase, test_data
+from soc.fu.alu.test.test_pipe_caller import get_cu_inputs
+from soc.fu.alu.test.test_pipe_caller import ALUTestCase # creates the tests
+
+from soc.fu.test.common import ALUHelpers
 from soc.fu.compunits.compunits import ALUFunctionUnit
 from soc.fu.compunits.test.test_compunit import TestRunner
+from soc.config.endian import bigendian
 
 
 class ALUTestRunner(TestRunner):
     def __init__(self, test_data):
-        super().__init__(test_data, ALUFunctionUnit, self)
+        super().__init__(test_data, ALUFunctionUnit, self,
+                         Function.ALU, bigendian)
 
     def get_cu_inputs(self, dec2, sim):
         """naming (res) must conform to ALUFunctionUnit input regspec
         """
-        res = {}
-
-        reg3_ok = yield dec2.e.read_reg3.ok
-        reg1_ok = yield dec2.e.read_reg1.ok
-        assert reg3_ok != reg1_ok
-        if reg3_ok:
-            data1 = yield dec2.e.read_reg3.data
-            res['a'] = sim.gpr(data1).value
-        elif reg1_ok:
-            data1 = yield dec2.e.read_reg1.data
-            res['a'] = sim.gpr(data1).value
-
-        reg2_ok = yield dec2.e.read_reg2.ok
-        if reg2_ok:
-            data2 = yield dec2.e.read_reg2.data
-            res['b'] = sim.gpr(data2).value
-
-        carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
-        carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
-        res['xer_ca'] = carry | (carry32<<1)
-        so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
-        res['xer_so'] = so
-
+        res = yield from get_cu_inputs(dec2, sim)
         return res
 
-    def check_cu_outputs(self, res, dec2, sim, code):
+    def check_cu_outputs(self, res, dec2, sim, alu, code):
         """naming (res) must conform to ALUFunctionUnit output regspec
         """
-        out_reg_valid = yield dec2.e.write_reg.ok
-        if out_reg_valid:
-            write_reg_idx = yield dec2.e.write_reg.data
-            expected = sim.gpr(write_reg_idx).value
-            cu_out = res['o']
-            print(f"expected {expected:x}, actual: {cu_out:x}")
-            self.assertEqual(expected, cu_out, code)
 
-        rc = yield dec2.e.rc.data
-        op = yield dec2.e.insn_type
+        rc = yield dec2.e.do.rc.data
+        op = yield dec2.e.do.insn_type
         cridx_ok = yield dec2.e.write_cr.ok
         cridx = yield dec2.e.write_cr.data
 
@@ -60,33 +36,25 @@ class ALUTestRunner(TestRunner):
             self.assertEqual(cridx_ok, 1, code)
             self.assertEqual(cridx, 0, code)
 
-        if cridx_ok:
-            cr_expected = sim.crl[cridx].get_range().value
-            cr_actual = res['cr0']
-            print ("CR", cridx, cr_expected, cr_actual)
-            self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
+        sim_o = {}
 
-        cry_out = yield dec2.e.output_carry
-        if cry_out:
-            expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
-            xer_ca = res['xer_ca']
-            real_carry = xer_ca & 0b1 # XXX CO not CO32
-            self.assertEqual(expected_carry, real_carry, code)
-            expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
-            real_carry32 = bool(xer_ca & 0b10) # XXX CO32
-            self.assertEqual(expected_carry32, real_carry32, code)
+        yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_xer_ov(sim_o, sim, alu, dec2)
+        yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_xer_so(sim_o, sim, alu, dec2)
 
-        # TODO
-        oe = yield dec2.e.oe.data
-        if oe:
-            xer_ov = res['xer_ov']
-            xer_so = res['xer_so']
+        ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
+        ALUHelpers.check_xer_ov(self, res, sim_o, code)
+        ALUHelpers.check_xer_ca(self, res, sim_o, code)
+        ALUHelpers.check_int_o(self, res, sim_o, code)
+        ALUHelpers.check_xer_so(self, res, sim_o, code)
 
 
 if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
-    suite.addTest(ALUTestRunner(test_data))
+    suite.addTest(ALUTestRunner(ALUTestCase.test_data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)