Merge remote-tracking branch 'upstream/master' into pr

[soc.git] / src / soc / fu / compunits / test / test_branch_compunit.py

diff --git a/src/soc/fu/compunits/test/test_branch_compunit.py b/src/soc/fu/compunits/test/test_branch_compunit.py
index 5b2820227be510012e9aedf3dc69aa153a9a0ea3..b8e7aa326032cb979da46db58c5d20b6bbcb2cea 100644 (file)
--- a/src/soc/fu/compunits/test/test_branch_compunit.py
+++ b/src/soc/fu/compunits/test/test_branch_compunit.py
@@ -1,12 +1,11 @@
 import unittest
-from soc.decoder.power_enums import (XER_bits, Function, spr_dict)
+from openpower.decoder.power_enums import (XER_bits, Function)
 
-# XXX bad practice: use of global variables
-from soc.fu.branch.test.test_pipe_caller import BranchTestCase
-from soc.fu.branch.test.test_pipe_caller import test_data
+from soc.fu.branch.test.test_pipe_caller import BranchTestCase, get_cu_inputs
 
 from soc.fu.compunits.compunits import BranchFunctionUnit
 from soc.fu.compunits.test.test_compunit import TestRunner
+from openpower.endian import bigendian
 
 
 """
@@ -17,42 +16,19 @@ from soc.fu.compunits.test.test_compunit import TestRunner
 class BranchTestRunner(TestRunner):
     def __init__(self, test_data):
         super().__init__(test_data, BranchFunctionUnit, self,
-                         Function.BRANCH)
+                         Function.BRANCH, bigendian)
 
     def get_cu_inputs(self, dec2, sim):
         """naming (res) must conform to BranchFunctionUnit input regspec
         """
-        res = {}
-        full_reg = yield dec2.e.read_cr_whole
-
-        # CIA (PC)
-        res['cia'] = sim.pc.CIA.value
-        # CR A
-        cr1_en = yield dec2.e.read_cr1.ok
-        if cr1_en:
-            cr1_sel = yield dec2.e.read_cr1.data
-            res['cr_a'] = sim.crl[cr1_sel].get_range().value
-
-        # SPR1
-        spr_ok = yield dec2.e.read_spr1.ok
-        spr_num = yield dec2.e.read_spr1.data
-        if spr_ok:
-            res['spr1'] = sim.spr[spr_dict[spr_num].SPR].value
-
-        # SPR2
-        spr_ok = yield dec2.e.read_spr2.ok
-        spr_num = yield dec2.e.read_spr2.data
-        if spr_ok:
-            res['spr2'] = sim.spr[spr_dict[spr_num].SPR].value
-
-        print ("get inputs", res)
+        res = yield from get_cu_inputs(dec2, sim)
         return res
 
-    def check_cu_outputs(self, res, dec2, sim, code):
+    def check_cu_outputs(self, res, dec2, sim, alu, code):
         """naming (res) must conform to BranchFunctionUnit output regspec
         """
 
-        print ("check extra output", repr(code), res)
+        print("check extra output", repr(code), res)
 
         # NIA (next instruction address aka PC)
         branch_taken = 'nia' in res
@@ -64,23 +40,24 @@ class BranchTestRunner(TestRunner):
             self.assertEqual(branch_addr, sim.pc.CIA.value, code)
 
         # Link SPR
-        lk = yield dec2.e.lk
-        branch_lk = 'spr2' in res
+        lk = yield dec2.e.do.lk
+        branch_lk = 'fast2' in res
         self.assertEqual(lk, branch_lk, code)
         if lk:
-            branch_lr = res['spr2']
+            branch_lr = res['fast2']
             self.assertEqual(sim.spr['LR'], branch_lr, code)
 
         # CTR SPR
-        ctr_ok = 'spr1' in res
+        ctr_ok = 'fast1' in res
         if ctr_ok:
-            ctr = res['spr1']
+            ctr = res['fast1']
             self.assertEqual(sim.spr['CTR'], ctr, code)
 
+
 if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
-    suite.addTest(BranchTestRunner(test_data))
+    suite.addTest(BranchTestRunner(BranchTestCase().test_data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)