Merge remote-tracking branch 'upstream/master' into pr

[soc.git] / src / soc / fu / compunits / test / test_branch_compunit.py

diff --git a/src/soc/fu/compunits/test/test_branch_compunit.py b/src/soc/fu/compunits/test/test_branch_compunit.py
index 622aabfd184e781ee8d20e9eab9452f786033195..b8e7aa326032cb979da46db58c5d20b6bbcb2cea 100644 (file)
--- a/src/soc/fu/compunits/test/test_branch_compunit.py
+++ b/src/soc/fu/compunits/test/test_branch_compunit.py
@@ -1,13 +1,12 @@
 import unittest
-from soc.decoder.power_enums import (XER_bits, Function, spr_dict, SPR)
+from openpower.decoder.power_enums import (XER_bits, Function)
 
-# XXX bad practice: use of global variables
 from soc.fu.branch.test.test_pipe_caller import BranchTestCase, get_cu_inputs
 
 from soc.fu.compunits.compunits import BranchFunctionUnit
 from soc.fu.compunits.test.test_compunit import TestRunner
+from openpower.endian import bigendian
 
-from soc.regfile.util import fast_reg_to_spr # HACK!
 
 """
     def assert_outputs(self, branch, dec2, sim, prev_nia, code):
@@ -17,7 +16,7 @@ from soc.regfile.util import fast_reg_to_spr # HACK!
 class BranchTestRunner(TestRunner):
     def __init__(self, test_data):
         super().__init__(test_data, BranchFunctionUnit, self,
-                         Function.BRANCH)
+                         Function.BRANCH, bigendian)
 
     def get_cu_inputs(self, dec2, sim):
         """naming (res) must conform to BranchFunctionUnit input regspec
@@ -25,11 +24,11 @@ class BranchTestRunner(TestRunner):
         res = yield from get_cu_inputs(dec2, sim)
         return res
 
-    def check_cu_outputs(self, res, dec2, sim, code):
+    def check_cu_outputs(self, res, dec2, sim, alu, code):
         """naming (res) must conform to BranchFunctionUnit output regspec
         """
 
-        print ("check extra output", repr(code), res)
+        print("check extra output", repr(code), res)
 
         # NIA (next instruction address aka PC)
         branch_taken = 'nia' in res
@@ -41,7 +40,7 @@ class BranchTestRunner(TestRunner):
             self.assertEqual(branch_addr, sim.pc.CIA.value, code)
 
         # Link SPR
-        lk = yield dec2.e.lk
+        lk = yield dec2.e.do.lk
         branch_lk = 'fast2' in res
         self.assertEqual(lk, branch_lk, code)
         if lk:
@@ -58,7 +57,7 @@ class BranchTestRunner(TestRunner):
 if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
-    suite.addTest(BranchTestRunner(BranchTestCase.test_data))
+    suite.addTest(BranchTestRunner(BranchTestCase().test_data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)