debug printout of sim and hardware memory, shows mismatch of depths

[soc.git] / src / soc / fu / compunits / test / test_compunit.py

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index a62a469480faa2f09dbab0e87c6db70cbe52ee8e..1265ba94ae1c785963a4a0ad585da4dca083fb89 100644 (file)
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -152,13 +152,11 @@ class TestRunner(FHDLTestCase):
                 # initialise memory
                 if self.funit == Function.LDST:
                     mem = l0.mem.mem
-                    memlist = []
                     for i in range(mem.depth//2):
                         data = sim.mem.ld(i*16, 8)
                         data1 = sim.mem.ld(i*16+8, 8)
                         yield mem._array[i].eq(data | (data1<<32))
-                    print (mem, mem.depth, mem.width)
-                    print ("mem init", list(map(hex,memlist)))
+                    print ("init mem", mem.depth, mem.width, mem)
 
                 index = sim.pc.CIA.value//4
                 while index < len(instructions):
@@ -199,7 +197,6 @@ class TestRunner(FHDLTestCase):
                     wr_rel_o = yield cu.wr.rel
                     print ("before inputs, rd_rel, wr_rel: ",
                             bin(rd_rel_o), bin(wr_rel_o))
-                    yield
                     assert wr_rel_o == 0, "wr.rel %s must be zero. "\
                                 "previous instr not written all regs\n"\
                                 "respec %s" % \
@@ -219,6 +216,11 @@ class TestRunner(FHDLTestCase):
                     yield Settle()
                     # get all outputs (one by one, just "because")
                     res = yield from get_cu_outputs(cu, code)
+                    wrmask = yield cu.wrmask
+                    rd_rel_o = yield cu.rd.rel
+                    wr_rel_o = yield cu.wr.rel
+                    print ("after got outputs, rd_rel, wr_rel, wrmask: ",
+                            bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
 
                     # wait for busy to go low
                     while True:
@@ -233,7 +235,24 @@ class TestRunner(FHDLTestCase):
 
                     # sigh.  hard-coded.  test memory
                     if self.funit == Function.LDST:
-                        print ("mem dump", sim.mem.mem)
+                        mem = l0.mem.mem
+                        print ("sim mem dump")
+                        for k, v in sim.mem.mem.items():
+                            print ("    %6x %016x" % (k, v))
+                        print ("nmigen mem dump")
+                        for i in range(mem.depth//2):
+                            actual_mem = yield mem._array[i]
+                            print ("    %6i %032x" % (i*2, actual_mem))
+
+                        for i in range(mem.depth//2):
+                            data = sim.mem.ld(i*16, 8)
+                            data1 = sim.mem.ld(i*16+8, 8)
+                            expected_mem = (data | (data1<<32))
+                            actual_mem = yield mem._array[i]
+                            self.assertEqual(expected_mem, actual_mem,
+                                    "%s %d %x %x" % (code, i,
+                                                     expected_mem, actual_mem))
+
 
         sim.add_sync_process(process)