add logical compunit test

[soc.git] / src / soc / fu / compunits / test / test_compunit.py

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 06aef9fe4d88e91c891d115758008520fcb0be79..62d2f2aaa9e4329c4ae1a75857038e5f4525c72e 100644 (file)
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -104,11 +104,12 @@ def get_cu_rd_mask(n_src, inp):
 
 
 class TestRunner(FHDLTestCase):
-    def __init__(self, test_data, fukls, iodef):
+    def __init__(self, test_data, fukls, iodef, funit):
         super().__init__("run_all")
         self.test_data = test_data
         self.fukls = fukls
-        self.iodef = iodef 
+        self.iodef = iodef
+        self.funit = funit
 
     def run_all(self):
         m = Module()
@@ -149,7 +150,7 @@ class TestRunner(FHDLTestCase):
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
                     fn_unit = yield pdecode2.e.fn_unit
-                    self.assertEqual(fn_unit, Function.ALU.value)
+                    self.assertEqual(fn_unit, self.funit.value)
 
                     # set operand and get inputs
                     yield from set_operand(cu, pdecode2, sim)