import unittest
from soc.decoder.power_enums import (XER_bits, Function)
-# XXX bad practice: use of global variables
-from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
-from soc.fu.logical.test.test_pipe_caller import test_data
+from soc.fu.logical.test.test_pipe_caller import (LogicalTestCase,
+ get_cu_inputs)
from soc.fu.compunits.compunits import LogicalFunctionUnit
from soc.fu.compunits.test.test_compunit import TestRunner
+from soc.fu.test.common import ALUHelpers
+from soc.config.endian import bigendian
class LogicalTestRunner(TestRunner):
def __init__(self, test_data):
super().__init__(test_data, LogicalFunctionUnit, self,
- Function.LOGICAL)
+ Function.LOGICAL, bigendian)
def get_cu_inputs(self, dec2, sim):
"""naming (res) must conform to LogicalFunctionUnit input regspec
"""
- res = {}
-
- # RA (or RC)
- reg1_ok = yield dec2.e.read_reg1.ok
- if reg1_ok:
- data1 = yield dec2.e.read_reg1.data
- res['ra'] = sim.gpr(data1).value
-
- # RB (or immediate)
- reg2_ok = yield dec2.e.read_reg2.ok
- if reg2_ok:
- data2 = yield dec2.e.read_reg2.data
- res['rb'] = sim.gpr(data2).value
-
+ res = yield from get_cu_inputs(dec2, sim)
return res
- def check_cu_outputs(self, res, dec2, sim, code):
+ def check_cu_outputs(self, res, dec2, sim, alu, code):
"""naming (res) must conform to LogicalFunctionUnit output regspec
"""
- # RT
- out_reg_valid = yield dec2.e.write_reg.ok
- if out_reg_valid:
- write_reg_idx = yield dec2.e.write_reg.data
- expected = sim.gpr(write_reg_idx).value
- cu_out = res['o']
- print(f"expected {expected:x}, actual: {cu_out:x}")
- self.assertEqual(expected, cu_out, code)
-
- rc = yield dec2.e.rc.data
- op = yield dec2.e.insn_type
+ rc = yield dec2.e.do.rc.data
+ op = yield dec2.e.do.insn_type
cridx_ok = yield dec2.e.write_cr.ok
cridx = yield dec2.e.write_cr.data
self.assertEqual(cridx_ok, 1, code)
self.assertEqual(cridx, 0, code)
- # CR (CR0-7)
- if cridx_ok:
- cr_expected = sim.crl[cridx].get_range().value
- cr_actual = res['cr_a']
- print ("CR", cridx, cr_expected, cr_actual)
- self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
+ sim_o = {}
+
+ yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
+ yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
- # XER.ca
- cry_out = yield dec2.e.output_carry
- if cry_out:
- expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
- xer_ca = res['xer_ca']
- real_carry = xer_ca & 0b1 # XXX CO not CO32
- self.assertEqual(expected_carry, real_carry, code)
- expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
- real_carry32 = bool(xer_ca & 0b10) # XXX CO32
- self.assertEqual(expected_carry32, real_carry32, code)
+ ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
+ ALUHelpers.check_int_o(self, res, sim_o, code)
if __name__ == "__main__":
unittest.main(exit=False)
suite = unittest.TestSuite()
- suite.addTest(LogicalTestRunner(test_data))
+ suite.addTest(LogicalTestRunner(LogicalTestCase.test_data))
runner = unittest.TextTestRunner()
runner.run(suite)