sorting out bigendian/littleendian including in qemu

[soc.git] / src / soc / fu / compunits / test / test_logical_compunit.py

diff --git a/src/soc/fu/compunits/test/test_logical_compunit.py b/src/soc/fu/compunits/test/test_logical_compunit.py
index b3d8a1f798a30b857f7ce6e768b0ecb8b54a374b..877f14c53813dfedbc7dd891a10ce53d33baa677 100644 (file)
--- a/src/soc/fu/compunits/test/test_logical_compunit.py
+++ b/src/soc/fu/compunits/test/test_logical_compunit.py
@@ -1,17 +1,19 @@
 import unittest
 from soc.decoder.power_enums import (XER_bits, Function)
 
-from soc.fu.logical.test.test_pipe_caller import LogicalTestCase, get_cu_inputs
+from soc.fu.logical.test.test_pipe_caller import (LogicalTestCase,
+                                                  get_cu_inputs)
 
 from soc.fu.compunits.compunits import LogicalFunctionUnit
 from soc.fu.compunits.test.test_compunit import TestRunner
 from soc.fu.test.common import ALUHelpers
+from soc.config.endian import bigendian
 
 
 class LogicalTestRunner(TestRunner):
     def __init__(self, test_data):
         super().__init__(test_data, LogicalFunctionUnit, self,
-                         Function.LOGICAL)
+                         Function.LOGICAL, bigendian)
 
     def get_cu_inputs(self, dec2, sim):
         """naming (res) must conform to LogicalFunctionUnit input regspec
@@ -19,12 +21,12 @@ class LogicalTestRunner(TestRunner):
         res = yield from get_cu_inputs(dec2, sim)
         return res
 
-    def check_cu_outputs(self, res, dec2, sim, code):
+    def check_cu_outputs(self, res, dec2, sim, alu, code):
         """naming (res) must conform to LogicalFunctionUnit output regspec
         """
 
-        rc = yield dec2.e.rc.data
-        op = yield dec2.e.insn_type
+        rc = yield dec2.e.do.rc.data
+        op = yield dec2.e.do.insn_type
         cridx_ok = yield dec2.e.write_cr.ok
         cridx = yield dec2.e.write_cr.data
 
@@ -37,7 +39,7 @@ class LogicalTestRunner(TestRunner):
         sim_o = {}
 
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 
         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
         ALUHelpers.check_int_o(self, res, sim_o, code)