rename get_sim_cr_a to get_wr_sim_cr_a for now

[soc.git] / src / soc / fu / compunits / test / test_logical_compunit.py

diff --git a/src/soc/fu/compunits/test/test_logical_compunit.py b/src/soc/fu/compunits/test/test_logical_compunit.py
index b3d8a1f798a30b857f7ce6e768b0ecb8b54a374b..e9a201e34047287c577069f43939b60927196c7e 100644 (file)
--- a/src/soc/fu/compunits/test/test_logical_compunit.py
+++ b/src/soc/fu/compunits/test/test_logical_compunit.py
@@ -37,7 +37,7 @@ class LogicalTestRunner(TestRunner):
         sim_o = {}
 
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 
         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
         ALUHelpers.check_int_o(self, res, sim_o, code)