clarify

[soc.git] / src / soc / fu / cr / cr_input_record.py

diff --git a/src/soc/fu/cr/cr_input_record.py b/src/soc/fu/cr/cr_input_record.py
index 1fadaf4eed1ed14f9ea8b2cc814ac6f84252a732..d5ffe87e2a527e5d54ce4df1b34b81dd526f350a 100644 (file)
--- a/src/soc/fu/cr/cr_input_record.py
+++ b/src/soc/fu/cr/cr_input_record.py
@@ -1,7 +1,6 @@
 from nmigen.hdl.rec import Record, Layout
 
-from soc.decoder.power_enums import (InternalOp, Function, CryIn,
-                                     CRInSel, CROutSel)
+from soc.decoder.power_enums import (InternalOp, Function)
 
 
 class CompCROpSubset(Record):
@@ -14,19 +13,19 @@ class CompCROpSubset(Record):
     def __init__(self, name=None):
         layout = (('insn_type', InternalOp),
                   ('fn_unit', Function),
-                  ('input_cr', CRInSel),
-                  ('output_cr', CROutSel),
-                  ('is_32bit', 1),
+                  ('insn', 32),
+                  ('read_cr_whole', 1),
+                  ('write_cr_whole', 1),
                   )
 
         Record.__init__(self, Layout(layout), name=name)
 
         # grrr.  Record does not have kwargs
         self.insn_type.reset_less = True
+        self.insn.reset_less = True
         self.fn_unit.reset_less = True
-        self.input_cr.reset_less = True
-        self.output_cr.reset_less = True
-        self.is_32bit.reset_less = True
+        self.read_cr_whole.reset_less = True
+        self.write_cr_whole.reset_less = True
 
     def eq_from_execute1(self, other):
         """ use this to copy in from Decode2Execute1Type
@@ -39,8 +38,8 @@ class CompCROpSubset(Record):
 
     def ports(self):
         return [self.insn_type,
+                self.insn,
                 self.fn_unit,
-                self.input_cr,
-                self.output_cr,
-                self.is_32bit,
+                self.read_cr_whole,
+                self.write_cr_whole,
         ]