link ST.go directly to ST.rel

[soc.git] / src / soc / fu / cr / pipe_data.py

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index 7a9e4422b824a605a9a8f39cae689f8d1dfd5a0f..06c7bfb7e8d209b4ed5570e35f71778b9c859901 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -1,53 +1,34 @@
-from nmigen import Signal, Const
-from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.pipe_data import IntegerData
-from nmutil.dynamicpipe import SimpleHandshakeRedir
-from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
+"""
+Links:
+* https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
+"""
+from soc.fu.pipe_data import IntegerData, CommonPipeSpec
+from soc.fu.cr.cr_input_record import CompCROpSubset
 
 
 class CRInputData(IntegerData):
-    regspec = [('INT', 'a', '0:63'),
-               ('CR', 'cr', '32')]
+    regspec = [('INT', 'ra', '0:63'),      # 64 bit range
+               ('INT', 'rb', '0:63'),      # 64 bit range
+               ('CR', 'full_cr', '0:31'), # 32 bit range
+               ('CR', 'cr_a', '0:3'),     # 4 bit range
+               ('CR', 'cr_b', '0:3'),     # 4 bit range
+               ('CR', 'cr_c', '0:3')]     # 4 bit: for CR_OP partial update
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.a = Signal(64, reset_less=True) # RA
-        self.cr = Signal(32, reset_less=True) # CR in
+        super().__init__(pspec, False)
+        # convenience
+        self.a, self.b = self.ra, self.rb
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.a
-        yield self.cr
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.a.eq(i.a),
-                      self.cr.eq(i.cr)]
 
 class CROutputData(IntegerData):
-    regspec = [('INT', 'o', '0:63'),
-               ('CR', 'cr', '32')]
+    regspec = [('INT', 'o', '0:63'),      # RA - 64 bit range
+               ('CR', 'full_cr', '0:31'), # 32 bit range
+               ('CR', 'cr_a', '0:3')]     # 4 bit range
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.o = Signal(64, reset_less=True) # RA
-        self.cr = Signal(32, reset_less=True, name="cr_out") # CR in
-
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.o
-        yield self.cr
+        super().__init__(pspec, True)
+        # convenience
+        self.cr = self.cr_a
 
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.o.eq(i.o),
-                      self.cr.eq(i.cr)]
 
-# TODO: replace CompALUOpSubset with CompCROpSubset
-class CRPipeSpec:
+class CRPipeSpec(CommonPipeSpec):
     regspec = (CRInputData.regspec, CROutputData.regspec)
-    opsubsetkls = CompALUOpSubset
-    def __init__(self, id_wid, op_wid):
-        self.id_wid = id_wid
-        self.op_wid = op_wid
-        self.opkls = lambda _: self.opsubsetkls(name="op")
-        self.stage = None
-        self.pipekls = SimpleHandshakeRedir
+    opsubsetkls = CompCROpSubset