convert to individual PipeSpecs for each pipeline

[soc.git] / src / soc / fu / cr / test / test_pipe_caller.py

diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index 415ce48e746e68e3a853299ae3e007974b089f2f..31da549669def3ebf89257607d095b3c2ff28161 100644 (file)
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -14,7 +14,7 @@ from soc.decoder.isa.all import ISA
 
 from soc.fu.cr.pipeline import CRBasePipe
 from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.fu.alu.pipe_data import ALUPipeSpec
+from soc.fu.cr.pipe_data import CRPipeSpec
 import random
 
 
@@ -117,9 +117,9 @@ class CRTestCase(FHDLTestCase):
         
 
     def test_ilang(self):
-        rec = CompALUOpSubset()
+        rec = CRPipeSpec.opsubsetkls()
 
-        pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+        pspec = CRPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = CRBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())
         with open("cr_pipeline.il", "w") as f:
@@ -149,9 +149,9 @@ class TestRunner(FHDLTestCase):
 
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 
-        rec = CompALUOpSubset()
+        rec = CRPipeSpec.opsubsetkls()
 
-        pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+        pspec = CRPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         m.submodules.alu = alu = CRBasePipe(pspec)
 
         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)