from soc.config.endian import bigendian
from soc.fu.test.common import TestAccumulatorBase, TestCase, ALUHelpers
+from soc.fu.test.common import mask_extend
from soc.fu.cr.pipeline import CRBasePipe
from soc.fu.cr.pipe_data import CRPipeSpec
import random
self.add_case(Program(lst, bigendian), initial_cr=cr)
def case_mtcrf(self):
- for i in range(20):
+ for i in range(1):
mask = random.randint(0, 255)
lst = [f"mtcrf {mask}, 2"]
cr = random.randint(0, (1 << 32)-1)
initial_cr=cr)
def case_mfcr(self):
- for i in range(5):
+ for i in range(1):
lst = ["mfcr 2"]
cr = random.randint(0, (1 << 32)-1)
self.add_case(Program(lst, bigendian), initial_cr=cr)
+ def case_cror_regression(self):
+ """another bad hack!
+ """
+ dis = ["cror 28, 5, 11"]
+ lst = bytes([0x83, 0x5b, 0x75, 0x4f]) # 4f855b83
+ cr = 0x35055058
+ p = Program(lst, bigendian)
+ p.assembly = '\n'.join(dis)+'\n'
+ self.add_case(p, initial_cr=cr)
+
+ def case_mfocrf_regression(self):
+ """bit of a bad hack. comes from microwatt 1.bin instruction 0x106d0
+ as the mask is non-standard, gnu-as barfs. so we fake it up directly
+ from the binary
+ """
+ mask = 0b10000111
+ dis = [f"mfocrf 2, {mask}"]
+ lst = bytes([0x26, 0x78, 0xb8, 0x7c]) # 0x7cb87826
+ cr = 0x5F9E080E
+ p = Program(lst, bigendian)
+ p.assembly = '\n'.join(dis)+'\n'
+ self.add_case(p, initial_cr=cr)
+
+ def case_mtocrf_regression(self):
+ """microwatt 1.bin regression, same hack as above.
+ 106b4: 21 d9 96 7d .long 0x7d96d921 # mtocrf 12, 0b01101101
+ """
+ mask = 0b01101101
+ dis = [f"mtocrf 12, {mask}"]
+ lst = bytes([0x21, 0xd9, 0x96, 0x7d]) # 0x7d96d921
+ cr = 0x529e08fe
+ initial_regs = [0] * 32
+ initial_regs[12] = 0xffffffffffffffff
+ p = Program(lst, bigendian)
+ p.assembly = '\n'.join(dis)+'\n'
+ self.add_case(p, initial_regs=initial_regs, initial_cr=cr)
+
+ def case_mtocrf_regression_2(self):
+ """microwatt 1.bin regression, zero fxm
+ mtocrf 0,16 14928: 21 09 10 7e .long 0x7e100921
+ """
+ dis = ["mtocrf 16, 0"]
+ lst = bytes([0x21, 0x09, 0x10, 0x7e]) # 0x7e100921
+ cr = 0x3F089F7F
+ initial_regs = [0] * 32
+ initial_regs[16] = 0x0001C020
+ p = Program(lst, bigendian)
+ p.assembly = '\n'.join(dis)+'\n'
+ self.add_case(p, initial_regs=initial_regs, initial_cr=cr)
+
+ def case_mfocrf_1(self):
+ lst = [f"mfocrf 2, 1"]
+ cr = 0x1234
+ self.add_case(Program(lst, bigendian), initial_cr=cr)
+
def case_mfocrf(self):
- for i in range(20):
+ for i in range(1):
mask = 1 << random.randint(0, 7)
lst = [f"mfocrf 2, {mask}"]
cr = random.randint(0, (1 << 32)-1)
self.add_case(Program(lst, bigendian), initial_cr=cr)
+ def case_isel_0(self):
+ lst = [ "isel 4, 1, 2, 31"
+ ]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1004
+ initial_regs[2] = 0x1008
+ cr= 0x1ee
+ self.add_case(Program(lst, bigendian),
+ initial_regs=initial_regs, initial_cr=cr)
+
+ def case_isel_1(self):
+ lst = [ "isel 4, 1, 2, 30"
+ ]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1004
+ initial_regs[2] = 0x1008
+ cr= 0x1ee
+ self.add_case(Program(lst, bigendian),
+ initial_regs=initial_regs, initial_cr=cr)
+
+ def case_isel_2(self):
+ lst = [ "isel 4, 1, 2, 2"
+ ]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1004
+ initial_regs[2] = 0x1008
+ cr= 0x1ee
+ self.add_case(Program(lst, bigendian),
+ initial_regs=initial_regs, initial_cr=cr)
+
+ def case_isel_3(self):
+ lst = [ "isel 1, 2, 3, 13"
+ ]
+ initial_regs = [0] * 32
+ initial_regs[2] = 0x1004
+ initial_regs[3] = 0x1008
+ cr= 0x5d677571b8229f1
+ cr= 0x1b8229f1
+ self.add_case(Program(lst, bigendian),
+ initial_regs=initial_regs, initial_cr=cr)
+
def case_isel(self):
for i in range(20):
bc = random.randint(0, 31)
lst = [f"isel 1, 2, 3, {bc}"]
- cr = random.randint(0, (1 << 32)-1)
+ cr = random.randint(0, (1 << 64)-1)
initial_regs = [0] * 32
- initial_regs[2] = random.randint(0, (1 << 64)-1)
- initial_regs[3] = random.randint(0, (1 << 64)-1)
- #initial_regs[2] = i*2
- #initial_regs[3] = i*2+1
+ #initial_regs[2] = random.randint(0, (1 << 64)-1)
+ #initial_regs[3] = random.randint(0, (1 << 64)-1)
+ initial_regs[2] = i*2+1
+ initial_regs[3] = i*2+2
self.add_case(Program(lst, bigendian),
initial_regs=initial_regs, initial_cr=cr)
"""naming (res) must conform to CRFunctionUnit input regspec
"""
res = {}
- full_reg = yield dec2.e.do.read_cr_whole
+ full_reg = yield dec2.dec_cr_in.whole_reg.data
+ full_reg_ok = yield dec2.dec_cr_in.whole_reg.ok
+ full_cr_mask = mask_extend(full_reg, 8, 4)
# full CR
- print(sim.cr.get_range().value)
- if full_reg:
- res['full_cr'] = sim.cr.get_range().value
+ print(sim.cr.value)
+ if full_reg_ok:
+ res['full_cr'] = sim.cr.value & full_cr_mask
else:
- # CR A
- cr1_en = yield dec2.e.read_cr1.ok
- if cr1_en:
- cr1_sel = yield dec2.e.read_cr1.data
- res['cr_a'] = sim.crl[cr1_sel].get_range().value
- cr2_en = yield dec2.e.read_cr2.ok
- # CR B
- if cr2_en:
- cr2_sel = yield dec2.e.read_cr2.data
- res['cr_b'] = sim.crl[cr2_sel].get_range().value
- cr3_en = yield dec2.e.read_cr3.ok
- # CR C
- if cr3_en:
- cr3_sel = yield dec2.e.read_cr3.data
- res['cr_c'] = sim.crl[cr3_sel].get_range().value
-
- # RA/RC
- reg1_ok = yield dec2.e.read_reg1.ok
- if reg1_ok:
- data1 = yield dec2.e.read_reg1.data
- res['ra'] = sim.gpr(data1).value
-
- # RB (or immediate)
- reg2_ok = yield dec2.e.read_reg2.ok
- if reg2_ok:
- data2 = yield dec2.e.read_reg2.data
- res['rb'] = sim.gpr(data2).value
+ yield from ALUHelpers.get_sim_cr_a(res, sim, dec2) # CR A
+ yield from ALUHelpers.get_sim_cr_b(res, sim, dec2) # CR B
+ yield from ALUHelpers.get_sim_cr_c(res, sim, dec2) # CR C
+
+ yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
+ yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
print("get inputs", res)
return res
yield from ALUHelpers.set_int_rb(alu, dec2, inp)
def assert_outputs(self, alu, dec2, simulator, code):
- whole_reg = yield dec2.e.do.write_cr_whole
+ whole_reg_ok = yield dec2.dec_cr_out.whole_reg.ok
+ whole_reg_data = yield dec2.dec_cr_out.whole_reg.data
+ full_cr_mask = mask_extend(whole_reg_data, 8, 4)
+
cr_en = yield dec2.e.write_cr.ok
- if whole_reg:
- full_cr = yield alu.n.data_o.full_cr.data
- expected_cr = simulator.cr.get_range().value
- print(f"CR whole: expected {expected_cr:x}, actual: {full_cr:x}")
- self.assertEqual(expected_cr, full_cr, code)
+ if whole_reg_ok:
+ full_cr = yield alu.n.data_o.full_cr.data & full_cr_mask
+ expected_cr = simulator.cr.value
+ print("CR whole: expected %x, actual: %x mask: %x" % \
+ (expected_cr, full_cr, full_cr_mask))
+ # HACK: only look at the bits that we expected to change
+ self.assertEqual(expected_cr & full_cr_mask, full_cr, code)
elif cr_en:
cr_sel = yield dec2.e.write_cr.data
- expected_cr = simulator.cr.get_range().value
+ expected_cr = simulator.cr.value
print(f"CR whole: {expected_cr:x}, sel {cr_sel}")
expected_cr = simulator.crl[cr_sel].get_range().value
real_cr = yield alu.n.data_o.cr.data
print(f"expected {expected:x}, actual: {alu_out:x}")
self.assertEqual(expected, alu_out, code)
+ def execute(self, alu, instruction, pdecode2, test):
+ program = test.program
+ sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
+ test.msr,
+ bigendian=bigendian)
+ gen = program.generate_instructions()
+ instructions = list(zip(gen, program.assembly.splitlines()))
+
+ index = sim.pc.CIA.value//4
+ while index < len(instructions):
+ ins, code = instructions[index]
+
+ print("0x{:X}".format(ins & 0xffffffff))
+ print(code)
+
+ # ask the decoder to decode this binary data (endian'd)
+ yield pdecode2.dec.bigendian.eq(bigendian) # little / big?
+ yield instruction.eq(ins) # raw binary instr.
+ yield Settle()
+ yield from self.set_inputs(alu, pdecode2, sim)
+ yield alu.p.valid_i.eq(1)
+ fn_unit = yield pdecode2.e.do.fn_unit
+ self.assertEqual(fn_unit, Function.CR.value, code)
+ yield
+ opname = code.split(' ')[0]
+ yield from sim.call(opname)
+ index = sim.pc.CIA.value//4
+
+ vld = yield alu.n.valid_o
+ while not vld:
+ yield
+ vld = yield alu.n.valid_o
+ yield
+ yield from self.assert_outputs(alu, pdecode2, sim, code)
+
def run_all(self):
m = Module()
comb = m.d.comb
instruction = Signal(32)
- pdecode = create_pdecode()
+ fn_name = "CR"
+ opkls = CRPipeSpec.opsubsetkls
- m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+ m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
+ pdecode = pdecode2.dec
pspec = CRPipeSpec(id_wid=2)
m.submodules.alu = alu = CRBasePipe(pspec)
def process():
for test in self.test_data:
print(test.name)
- program = test.program
- self.subTest(test.name)
- sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
- test.msr,
- bigendian=bigendian)
- gen = program.generate_instructions()
- instructions = list(zip(gen, program.assembly.splitlines()))
-
- index = sim.pc.CIA.value//4
- while index < len(instructions):
- ins, code = instructions[index]
-
- print("0x{:X}".format(ins & 0xffffffff))
- print(code)
-
- # ask the decoder to decode this binary data (endian'd)
- yield pdecode2.dec.bigendian.eq(bigendian) # little / big?
- yield instruction.eq(ins) # raw binary instr.
- yield Settle()
- yield from self.set_inputs(alu, pdecode2, sim)
- yield alu.p.valid_i.eq(1)
- fn_unit = yield pdecode2.e.do.fn_unit
- self.assertEqual(fn_unit, Function.CR.value, code)
- yield
- opname = code.split(' ')[0]
- yield from sim.call(opname)
- index = sim.pc.CIA.value//4
-
- vld = yield alu.n.valid_o
- while not vld:
- yield
- vld = yield alu.n.valid_o
- yield
- yield from self.assert_outputs(alu, pdecode2, sim, code)
+ with self.subTest(test.name):
+ yield from self.execute(alu, instruction, pdecode2, test)
sim.add_sync_process(process)
- with sim.write_vcd("simulator.vcd", "simulator.gtkw",
- traces=[]):
+ with sim.write_vcd("cr_simulator.vcd"):
sim.run()
projects / soc.git / blobdiff