remove xer_ca from DIV pipeline (took a bit of messing about)

[soc.git] / src / soc / fu / div / core_stages.py

diff --git a/src/soc/fu/div/core_stages.py b/src/soc/fu/div/core_stages.py
index 3bbde7dba509721545a51a6d223974091db3fc28..fdbe8659583b01a2073db5e01aae137c965286fa 100644 (file)
--- a/src/soc/fu/div/core_stages.py
+++ b/src/soc/fu/div/core_stages.py
@@ -3,14 +3,14 @@
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
-from soc.fu.logical.pipe_data import LogicalInputData
-from soc.fu.alu.pipe_data import ALUOutputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.decoder.power_enums import InternalOp
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
-from soc.fu.div.pipe_data import CoreInputData, CoreInterstageData, CoreOutputData
+from soc.fu.div.pipe_data import (CoreInputData,
+                                  CoreInterstageData,
+                                  CoreOutputData)
 from ieee754.div_rem_sqrt_rsqrt.core import (DivPipeCoreSetupStage,
                                              DivPipeCoreCalculateStage,
                                              DivPipeCoreFinalStage)