too much debug info going past, so add the test registers to the

[soc.git] / src / soc / fu / div / core_stages.py

diff --git a/src/soc/fu/div/core_stages.py b/src/soc/fu/div/core_stages.py
index aa53845abc6941f03631502d45bf9cd38a43d63c..fc1d7520e0b094a0b8c32da2d026bd65c9a7cb15 100644 (file)
--- a/src/soc/fu/div/core_stages.py
+++ b/src/soc/fu/div/core_stages.py
@@ -41,7 +41,8 @@ class DivCoreBaseStage(PipeModBase):
 
 class DivCoreSetupStage(DivCoreBaseStage):
     def __init__(self, pspec):
-        super().__init__(pspec, "core_setup_stage", DivPipeCoreSetupStage)
+        super().__init__(pspec, "core_setup_stage",
+                         pspec.div_pipe_kind.config.core_setup_stage_class)
 
     def ispec(self):
         return CoreInputData(self.pspec)
@@ -52,8 +53,9 @@ class DivCoreSetupStage(DivCoreBaseStage):
 
 class DivCoreCalculateStage(DivCoreBaseStage):
     def __init__(self, pspec, stage_index):
+        stage = pspec.div_pipe_kind.config.core_calculate_stage_class
         super().__init__(pspec, f"core_calculate_stage_{stage_index}",
-                         DivPipeCoreCalculateStage, stage_index)
+                         stage, stage_index)
 
     def ispec(self):
         return CoreInterstageData(self.pspec)
@@ -64,7 +66,8 @@ class DivCoreCalculateStage(DivCoreBaseStage):
 
 class DivCoreFinalStage(DivCoreBaseStage):
     def __init__(self, pspec):
-        super().__init__(pspec, "core_final_stage", DivPipeCoreFinalStage)
+        super().__init__(pspec, "core_final_stage",
+                         pspec.div_pipe_kind.config.core_final_stage_class)
 
     def ispec(self):
         return CoreInterstageData(self.pspec)