too much debug info going past, so add the test registers to the

[soc.git] / src / soc / fu / div / output_stage.py

diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py
index 4970a8070220cd78bbbc366bbd9941812335abff..0fc31c391414b89228d62b3300f4217e9f69774f 100644 (file)
--- a/src/soc/fu/div/output_stage.py
+++ b/src/soc/fu/div/output_stage.py
@@ -111,6 +111,7 @@ class DivOutputStage(PipeModBase):
         ##########################
         # main switch for Div
 
+        comb += self.o.o.ok.eq(1)
         o = self.o.o.data
 
         with m.If(~ov):  # result is valid (no overflow)