from soc.fu.logical.pipe_data import LogicalInputData
from soc.fu.div.pipe_data import DivMulOutputData
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.decoder.power_fields import DecodeFields
from soc.decoder.power_fieldsn import SignalBitRange
self.fields.create_specs()
self.quotient_neg = Signal()
self.remainder_neg = Signal()
- self.quotient_65 = Signal(65) # one extra spare bit for overflow
+ self.quotient_65 = Signal(65) # one extra spare bit for overflow
self.remainder_64 = Signal(64)
def ispec(self):
ov = Signal(reset_less=True)
with m.If(op.is_signed):
comb += ov.eq(overflow
- | (abs_quotient > sign_bit_mask)
- | ((abs_quotient == sign_bit_mask)
- & ~self.quotient_neg))
+ | (abs_quotient > sign_bit_mask)
+ | ((abs_quotient == sign_bit_mask)
+ & ~self.quotient_neg))
with m.Else():
comb += ov.eq(overflow)
- comb += xer_ov.eq(Repl(ov, 2)) # set OV _and_ OV32
+ comb += xer_ov.eq(Repl(ov, 2)) # set OV _and_ OV32
# check 32/64 bit version of overflow
with m.If(op.is_32bit):
comb += ov.eq(1)
with m.Else():
comb += ov.eq(self.i.dive_abs_ov32)
- comb += xer_ov.eq(Repl(ov, 2)) # set OV _and_ OV32
+ comb += xer_ov.eq(Repl(ov, 2)) # set OV _and_ OV32
##########################
- # main switch for DIV
+ # main switch for Div
+ comb += self.o.o.ok.eq(1)
o = self.o.o.data
- with m.Switch(op.insn_type):
- with m.Case(InternalOp.OP_DIVE):
- with m.If(op.is_32bit):
- with m.If(op.is_signed):
- # matches POWER9's divweo behavior
- comb += o.eq(quotient_65[0:32].as_unsigned())
+ with m.If(~ov): # result is valid (no overflow)
+ with m.Switch(op.insn_type):
+ with m.Case(MicrOp.OP_DIVE):
+ with m.If(op.is_32bit):
+ with m.If(op.is_signed):
+ # matches POWER9's divweo behavior
+ comb += o.eq(quotient_65[0:32].as_unsigned())
+ with m.Else():
+ comb += o.eq(quotient_65[0:32].as_unsigned())
with m.Else():
- comb += o.eq(quotient_65[0:32].as_unsigned())
- with m.Else():
- comb += o.eq(quotient_65)
- with m.Case(InternalOp.OP_DIV):
- with m.If(op.is_32bit):
- with m.If(op.is_signed):
- # matches POWER9's divwo behavior
- comb += o.eq(quotient_65[0:32].as_unsigned())
+ comb += o.eq(quotient_65)
+ with m.Case(MicrOp.OP_DIV):
+ with m.If(op.is_32bit):
+ with m.If(op.is_signed):
+ # matches POWER9's divwo behavior
+ comb += o.eq(quotient_65[0:32].as_unsigned())
+ with m.Else():
+ comb += o.eq(quotient_65[0:32].as_unsigned())
with m.Else():
- comb += o.eq(quotient_65[0:32].as_unsigned())
- with m.Else():
- comb += o.eq(quotient_65)
- with m.Case(InternalOp.OP_MOD):
- with m.If(op.is_32bit):
- with m.If(op.is_signed):
- # matches POWER9's modsw behavior
- comb += o.eq(remainder_64[0:32].as_signed())
+ comb += o.eq(quotient_65)
+ with m.Case(MicrOp.OP_MOD):
+ with m.If(op.is_32bit):
+ with m.If(op.is_signed):
+ # matches POWER9's modsw behavior
+ comb += o.eq(remainder_64[0:32].as_signed())
+ with m.Else():
+ comb += o.eq(remainder_64[0:32].as_unsigned())
with m.Else():
- comb += o.eq(remainder_64[0:32].as_unsigned())
- with m.Else():
- comb += o.eq(remainder_64)
+ comb += o.eq(remainder_64)
###### sticky overflow and context, both pass-through #####