too much debug info going past, so add the test registers to the

[soc.git] / src / soc / fu / div / output_stage.py

diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py
index b5b286a695475c06b8700bdbff8dd611b02c47f8..0fc31c391414b89228d62b3300f4217e9f69774f 100644 (file)
--- a/src/soc/fu/div/output_stage.py
+++ b/src/soc/fu/div/output_stage.py
@@ -9,7 +9,7 @@ from nmutil.pipemodbase import PipeModBase
 from soc.fu.logical.pipe_data import LogicalInputData
 from soc.fu.div.pipe_data import DivMulOutputData
 from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
@@ -23,7 +23,7 @@ class DivOutputStage(PipeModBase):
         self.fields.create_specs()
         self.quotient_neg = Signal()
         self.remainder_neg = Signal()
-        self.quotient_65 = Signal(65) # one extra spare bit for overflow
+        self.quotient_65 = Signal(65)  # one extra spare bit for overflow
         self.remainder_64 = Signal(64)
 
     def ispec(self):
@@ -79,12 +79,12 @@ class DivOutputStage(PipeModBase):
             ov = Signal(reset_less=True)
             with m.If(op.is_signed):
                 comb += ov.eq(overflow
-                                  | (abs_quotient > sign_bit_mask)
-                                  | ((abs_quotient == sign_bit_mask)
-                                     & ~self.quotient_neg))
+                              | (abs_quotient > sign_bit_mask)
+                              | ((abs_quotient == sign_bit_mask)
+                                 & ~self.quotient_neg))
             with m.Else():
                 comb += ov.eq(overflow)
-            comb += xer_ov.eq(Repl(ov, 2)) # set OV _and_ OV32
+            comb += xer_ov.eq(Repl(ov, 2))  # set OV _and_ OV32
 
         # check 32/64 bit version of overflow
         with m.If(op.is_32bit):
@@ -106,16 +106,17 @@ class DivOutputStage(PipeModBase):
                 comb += ov.eq(1)
         with m.Else():
             comb += ov.eq(self.i.dive_abs_ov32)
-        comb += xer_ov.eq(Repl(ov, 2)) # set OV _and_ OV32
+        comb += xer_ov.eq(Repl(ov, 2))  # set OV _and_ OV32
 
         ##########################
-        # main switch for DIV
+        # main switch for Div
 
+        comb += self.o.o.ok.eq(1)
         o = self.o.o.data
 
-        with m.If(~ov): # result is valid (no overflow)
+        with m.If(~ov):  # result is valid (no overflow)
             with m.Switch(op.insn_type):
-                with m.Case(InternalOp.OP_DIVE):
+                with m.Case(MicrOp.OP_DIVE):
                     with m.If(op.is_32bit):
                         with m.If(op.is_signed):
                             # matches POWER9's divweo behavior
@@ -124,7 +125,7 @@ class DivOutputStage(PipeModBase):
                             comb += o.eq(quotient_65[0:32].as_unsigned())
                     with m.Else():
                         comb += o.eq(quotient_65)
-                with m.Case(InternalOp.OP_DIV):
+                with m.Case(MicrOp.OP_DIV):
                     with m.If(op.is_32bit):
                         with m.If(op.is_signed):
                             # matches POWER9's divwo behavior
@@ -133,7 +134,7 @@ class DivOutputStage(PipeModBase):
                             comb += o.eq(quotient_65[0:32].as_unsigned())
                     with m.Else():
                         comb += o.eq(quotient_65)
-                with m.Case(InternalOp.OP_MOD):
+                with m.Case(MicrOp.OP_MOD):
                     with m.If(op.is_32bit):
                         with m.If(op.is_signed):
                             # matches POWER9's modsw behavior