too much debug info going past, so add the test registers to the

[soc.git] / src / soc / fu / div / pipe_data.py

diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py
index 000ac0a9abb0f9f3167a4c777fa6d9ddb7561955..c8279f42ade1fa4b7932438d27cd8205db0a2dd3 100644 (file)
--- a/src/soc/fu/div/pipe_data.py
+++ b/src/soc/fu/div/pipe_data.py
@@ -138,6 +138,21 @@ class DivPipeSpec(CommonPipeSpec):
     opsubsetkls = CompLogicalOpSubset
 
 
+class DivPipeSpecDivPipeCore(DivPipeSpec):
+    def __init__(self, id_wid):
+        super().__init__(id_wid=id_wid, div_pipe_kind=DivPipeKind.DivPipeCore)
+
+
+class DivPipeSpecFSMDivCore(DivPipeSpec):
+    def __init__(self, id_wid):
+        super().__init__(id_wid=id_wid, div_pipe_kind=DivPipeKind.FSMDivCore)
+
+
+class DivPipeSpecSimOnly(DivPipeSpec):
+    def __init__(self, id_wid):
+        super().__init__(id_wid=id_wid, div_pipe_kind=DivPipeKind.SimOnly)
+
+
 class CoreBaseData(DivInputData):
     def __init__(self, pspec, core_data_class):
         super().__init__(pspec)