too much debug info going past, so add the test registers to the

[soc.git] / src / soc / fu / div / setup_stage.py

diff --git a/src/soc/fu/div/setup_stage.py b/src/soc/fu/div/setup_stage.py
index 11619fc7d22c78f5a218e9bb8468a0b6d47ad5e5..8928f25cfc347a78594ecf7363442cf4140a8475 100644 (file)
--- a/src/soc/fu/div/setup_stage.py
+++ b/src/soc/fu/div/setup_stage.py
@@ -3,7 +3,7 @@
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
-from soc.fu.div.pipe_data import DIVInputData
+from soc.fu.div.pipe_data import DivInputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.decoder.power_enums import MicrOp
 
@@ -21,7 +21,7 @@ class DivSetupStage(PipeModBase):
         self.fields.create_specs()
 
     def ispec(self):
-        return DIVInputData(self.pspec)
+        return DivInputData(self.pspec)
 
     def ospec(self):
         return CoreInputData(self.pspec)
@@ -41,14 +41,15 @@ class DivSetupStage(PipeModBase):
         comb += core_o.operation.eq(int(DivPipeCoreOperation.UDivRem))
 
         # work out if a/b are negative (check 32-bit / signed)
-        comb += dividend_neg_o.eq(Mux(op.is_32bit, a[31], a[63]) & op.is_signed)
+        comb += dividend_neg_o.eq(Mux(op.is_32bit,
+                                      a[31], a[63]) & op.is_signed)
         comb += divisor_neg_o.eq(Mux(op.is_32bit, b[31], b[63]) & op.is_signed)
 
         # negation of a 64-bit value produces the same lower 32-bit
         # result as negation of just the lower 32-bits, so we don't
         # need to do anything special before negating
-        abs_dor = Signal(64, reset_less=True) # absolute of divisor
-        abs_dend = Signal(64, reset_less=True) # absolute of dividend
+        abs_dor = Signal(64, reset_less=True)  # absolute of divisor
+        abs_dend = Signal(64, reset_less=True)  # absolute of dividend
         comb += abs_dor.eq(Mux(divisor_neg_o, -b, b))
         comb += abs_dend.eq(Mux(dividend_neg_o, -a, a))
 
@@ -66,7 +67,7 @@ class DivSetupStage(PipeModBase):
         comb += self.o.div_by_zero.eq(divisor_o == 0)
 
         ##########################
-        # main switch for DIV
+        # main switch for Div
 
         with m.Switch(op.insn_type):
             # div/mod takes straight (absolute) dividend