convert branch pipeline to use msr/cia as immediates

[soc.git] / src / soc / fu / div / setup_stage.py

diff --git a/src/soc/fu/div/setup_stage.py b/src/soc/fu/div/setup_stage.py
index 679c9cc61c9973d17a344cd1a9595a530dd31011..8928f25cfc347a78594ecf7363442cf4140a8475 100644 (file)
--- a/src/soc/fu/div/setup_stage.py
+++ b/src/soc/fu/div/setup_stage.py
@@ -3,7 +3,7 @@
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
-from soc.fu.div.pipe_data import DIVInputData
+from soc.fu.div.pipe_data import DivInputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.decoder.power_enums import MicrOp
 
@@ -21,7 +21,7 @@ class DivSetupStage(PipeModBase):
         self.fields.create_specs()
 
     def ispec(self):
-        return DIVInputData(self.pspec)
+        return DivInputData(self.pspec)
 
     def ospec(self):
         return CoreInputData(self.pspec)
@@ -67,7 +67,7 @@ class DivSetupStage(PipeModBase):
         comb += self.o.div_by_zero.eq(divisor_o == 0)
 
         ##########################
-        # main switch for DIV
+        # main switch for Div
 
         with m.Switch(op.insn_type):
             # div/mod takes straight (absolute) dividend