from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
from nmutil.pipemodbase import PipeModBase
-from soc.fu.div.pipe_data import DIVInputData
-from soc.fu.alu.pipe_data import ALUOutputData
+from soc.fu.div.pipe_data import DivInputData
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.decoder.power_fields import DecodeFields
from soc.decoder.power_fieldsn import SignalBitRange
from soc.fu.div.pipe_data import CoreInputData
from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreOperation
-
-def eq32(is_32bit, dest, src):
- return [dest[0:32].eq(src[0:32]),
- dest[32:64].eq(Mux(is_32bit, 0, src[32:64]))]
+from nmutil.util import eq32
class DivSetupStage(PipeModBase):
self.fields.create_specs()
def ispec(self):
- return DIVInputData(self.pspec)
+ return DivInputData(self.pspec)
def ospec(self):
return CoreInputData(self.pspec)
comb += core_o.operation.eq(int(DivPipeCoreOperation.UDivRem))
# work out if a/b are negative (check 32-bit / signed)
- comb += dividend_neg_o.eq(Mux(op.is_32bit, a[31], a[63]) & op.is_signed)
+ comb += dividend_neg_o.eq(Mux(op.is_32bit,
+ a[31], a[63]) & op.is_signed)
comb += divisor_neg_o.eq(Mux(op.is_32bit, b[31], b[63]) & op.is_signed)
# negation of a 64-bit value produces the same lower 32-bit
# result as negation of just the lower 32-bits, so we don't
# need to do anything special before negating
- abs_dor = Signal(64, reset_less=True) # absolute of divisor
- abs_dend = Signal(64, reset_less=True) # absolute of dividend
+ abs_dor = Signal(64, reset_less=True) # absolute of divisor
+ abs_dend = Signal(64, reset_less=True) # absolute of dividend
comb += abs_dor.eq(Mux(divisor_neg_o, -b, b))
comb += abs_dend.eq(Mux(dividend_neg_o, -a, a))
# check for absolute overflow condition (32/64)
comb += self.o.dive_abs_ov64.eq((abs_dend >= abs_dor)
- & (op.insn_type == InternalOp.OP_DIVE))
+ & (op.insn_type == MicrOp.OP_DIVE))
comb += self.o.dive_abs_ov32.eq((abs_dend[0:32] >= abs_dor[0:32])
- & (op.insn_type == InternalOp.OP_DIVE))
+ & (op.insn_type == MicrOp.OP_DIVE))
# set divisor based on 32/64 bit mode (must be absolute)
comb += eq32(op.is_32bit, divisor_o, abs_dor)
comb += self.o.div_by_zero.eq(divisor_o == 0)
##########################
- # main switch for DIV
+ # main switch for Div
with m.Switch(op.insn_type):
# div/mod takes straight (absolute) dividend
- with m.Case(InternalOp.OP_DIV, InternalOp.OP_MOD):
+ with m.Case(MicrOp.OP_DIV, MicrOp.OP_MOD):
comb += eq32(op.is_32bit, dividend_o, abs_dend)
# extended div shifts dividend up
- with m.Case(InternalOp.OP_DIVE):
+ with m.Case(MicrOp.OP_DIVE):
with m.If(op.is_32bit):
comb += dividend_o.eq(abs_dend[0:32] << 32)
with m.Else():