move over to from openpower imports

[soc.git] / src / soc / fu / div / test / helper.py

diff --git a/src/soc/fu/div/test/helper.py b/src/soc/fu/div/test/helper.py
index 5be75e64b9c4fc58901926ac15d8bf3272977273..7c4f9d6915dc15c95cc0b2263f026f1e99637dcf 100644 (file)
--- a/src/soc/fu/div/test/helper.py
+++ b/src/soc/fu/div/test/helper.py
@@ -7,10 +7,10 @@ from nmigen import Module, Signal
 # Also, check out the cxxsim nmigen branch, and latest yosys from git
 from nmutil.sim_tmp_alternative import Simulator, Delay
 
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import XER_bits, Function
-from soc.decoder.isa.all import ISA
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import XER_bits, Function
+from openpower.decoder.isa.all import ISA
 from soc.config.endian import bigendian
 
 from soc.fu.test.common import ALUHelpers