use correct ALUHelpers in div test

[soc.git] / src / soc / fu / div / test / test_pipe_caller.py

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 5571571b0d920b69e438b4c127334519d7af437b..25dedf8b1052d6a34179c2026af02efe24987f3b 100644 (file)
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -25,7 +25,7 @@ def get_cu_inputs(dec2, sim):
 
     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
-    yield from ALUHelpers.get_sim_xer_ca(res, sim, dec2) # XER.ca
+    yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca
     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
 
     print ("alu get_cu_inputs", res)
@@ -77,38 +77,8 @@ class DIVTestCase(FHDLTestCase):
         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
         self.test_data.append(tc)
 
-    def test_1_regression(self):
-        lst = [f"extsw 3, 1"]
-        initial_regs = [0] * 32
-        initial_regs[1] = 0xb6a1fc6c8576af91
-        self.run_tst_program(Program(lst), initial_regs)
-        lst = [f"subf 3, 1, 2"]
-        initial_regs = [0] * 32
-        initial_regs[1] = 0x3d7f3f7ca24bac7b
-        initial_regs[2] = 0xf6b2ac5e13ee15c2
-        self.run_tst_program(Program(lst), initial_regs)
-        lst = [f"subf 3, 1, 2"]
-        initial_regs = [0] * 32
-        initial_regs[1] = 0x833652d96c7c0058
-        initial_regs[2] = 0x1c27ecff8a086c1a
-        self.run_tst_program(Program(lst), initial_regs)
-        lst = [f"extsb 3, 1"]
-        initial_regs = [0] * 32
-        initial_regs[1] = 0x7f9497aaff900ea0
-        self.run_tst_program(Program(lst), initial_regs)
-        lst = [f"add. 3, 1, 2"]
-        initial_regs = [0] * 32
-        initial_regs[1] = 0xc523e996a8ff6215
-        initial_regs[2] = 0xe1e5b9cc9864c4a8
-        self.run_tst_program(Program(lst), initial_regs)
-        lst = [f"add 3, 1, 2"]
-        initial_regs = [0] * 32
-        initial_regs[1] = 0x2e08ae202742baf8
-        initial_regs[2] = 0x86c43ece9efe5baa
-        self.run_tst_program(Program(lst), initial_regs)
-
-    def test_rand(self):
-        insns = ["add", "add.", "subf"]
+    def test_rand_divw(self):
+        insns = ["divw", "divw.", "divwo", "divwo."]
         for i in range(40):
             choice = random.choice(insns)
             lst = [f"{choice} 3, 1, 2"]
@@ -117,55 +87,6 @@ class DIVTestCase(FHDLTestCase):
             initial_regs[2] = random.randint(0, (1<<64)-1)
             self.run_tst_program(Program(lst), initial_regs)
 
-    def test_rand_imm(self):
-        insns = ["addi", "addis", "subfic"]
-        for i in range(10):
-            choice = random.choice(insns)
-            imm = random.randint(-(1<<15), (1<<15)-1)
-            lst = [f"{choice} 3, 1, {imm}"]
-            print(lst)
-            initial_regs = [0] * 32
-            initial_regs[1] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
-
-    def test_0_adde(self):
-        lst = ["adde. 5, 6, 7"]
-        for i in range(10):
-            initial_regs = [0] * 32
-            initial_regs[6] = random.randint(0, (1<<64)-1)
-            initial_regs[7] = random.randint(0, (1<<64)-1)
-            initial_sprs = {}
-            xer = SelectableInt(0, 64)
-            xer[XER_bits['CA']] = 1
-            initial_sprs[special_sprs['XER']] = xer
-            self.run_tst_program(Program(lst), initial_regs, initial_sprs)
-
-    def test_cmp(self):
-        lst = ["subf. 1, 6, 7",
-               "cmp cr2, 1, 6, 7"]
-        initial_regs = [0] * 32
-        initial_regs[6] = 0x10
-        initial_regs[7] = 0x05
-        self.run_tst_program(Program(lst), initial_regs, {})
-
-    def test_extsb(self):
-        insns = ["extsb", "extsh", "extsw"]
-        for i in range(10):
-            choice = random.choice(insns)
-            lst = [f"{choice} 3, 1"]
-            print(lst)
-            initial_regs = [0] * 32
-            initial_regs[1] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
-
-    def test_cmpeqb(self):
-        lst = ["cmpeqb cr1, 1, 2"]
-        for i in range(20):
-            initial_regs = [0] * 32
-            initial_regs[1] = i
-            initial_regs[2] = 0x0001030507090b0f
-            self.run_tst_program(Program(lst), initial_regs, {})
-
     def test_ilang(self):
         pspec = DIVPipeSpec(id_wid=2)
         alu = DIVBasePipe(pspec)
@@ -276,7 +197,7 @@ class TestRunner(FHDLTestCase):
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 
         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))