add debugging chain for #425

[soc.git] / src / soc / fu / div / test / test_pipe_caller.py

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 6b80fcc1fc300e5508f32e2222143f677f14fb98..403c0b57e642311446511dcf8501ecf56ef81c40 100644 (file)
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -217,6 +217,7 @@ class TestRunner(FHDLTestCase):
                     while not vld:
                         yield
                         vld = yield alu.n.valid_o
+                        print ("bug track", alu.pipe_end.div_out)
                     yield
 
                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)