update code-comments

[soc.git] / src / soc / fu / ldst / loadstore.py

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index 5c43ebc66cef05c7871e1736e9c1e3dd2a774ac8..0397f87d1488c812b0b40bca31132873d2fd920b 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -1,3 +1,13 @@
+"""LoadStore1 FSM.
+
+based on microwatt loadstore1.vhdl
+
+Links:
+
+* https://bugs.libre-soc.org/show_bug.cgi?id=465
+
+"""
+
 from nmigen import (Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux,
                     Record, Memory,
                     Const)