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loadstore.py: add debug output for dcbz
[soc.git]
/
src
/
soc
/
fu
/
ldst
/
loadstore.py
diff --git
a/src/soc/fu/ldst/loadstore.py
b/src/soc/fu/ldst/loadstore.py
index 7400c0ae6eeefacfc92ae9c2783d2c9da5269d52..22acd797b05ef31a73d2dc93494f377c3b6d5eed 100644
(file)
--- a/
src/soc/fu/ldst/loadstore.py
+++ b/
src/soc/fu/ldst/loadstore.py
@@
-128,6
+128,8
@@
class LoadStore1(PortInterfaceBase):
m.d.comb += self.req.align_intr.eq(misalign)
m.d.comb += self.req.dcbz.eq(is_dcbz)
+ m.d.comb += Display("set_wr_addr %i dcbz %i",addr,is_dcbz)
+
# option to disable the cache entirely for write
if self.disable_cache:
m.d.comb += self.req.nc.eq(1)