add std and stdu ldst unit tests

[soc.git] / src / soc / fu / ldst / test / test_pipe_caller.py

diff --git a/src/soc/fu/ldst/test/test_pipe_caller.py b/src/soc/fu/ldst/test/test_pipe_caller.py
index 99ea01b29532eda736ea249914c7c47c006e9ea2..6336f0ae61141f7a6f8a5dd1554dd0b37be3ddef 100644 (file)
--- a/src/soc/fu/ldst/test/test_pipe_caller.py
+++ b/src/soc/fu/ldst/test/test_pipe_caller.py
@@ -10,6 +10,7 @@ from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
+from soc.config.endian import bigendian
 
 
 from soc.fu.test.common import TestCase
@@ -41,7 +42,7 @@ def get_cu_inputs(dec2, sim):
         res['rc'] = sim.gpr(data3).value
 
     # XER.so
-    oe = yield dec2.e.oe.data[0] & dec2.e.oe.ok
+    oe = yield dec2.e.do.oe.data[0] & dec2.e.do.oe.ok
     if oe:
         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
         res['xer_so'] = so
@@ -68,10 +69,10 @@ class LDSTTestCase(FHDLTestCase):
         initial_regs[1] = 0x0004
         initial_regs[2] = 0x0008
         initial_mem = {0x0000: (0x5432123412345678, 8),
-                       0x0010: (0xabcdef0187654321, 8),
-                       0x0040: (0x1828384822324252, 8),
+                       0x0008: (0xabcdef0187654321, 8),
+                       0x0020: (0x1828384822324252, 8),
                         }
-        self.run_tst_program(Program(lst), initial_regs,
+        self.run_tst_program(Program(lst, bigendian), initial_regs,
                              initial_mem=initial_mem)
 
     def test_2_load_store(self):
@@ -84,10 +85,10 @@ class LDSTTestCase(FHDLTestCase):
         initial_regs[2] = 0x0008
         initial_regs[3] = 0x00ee
         initial_mem = {0x0000: (0x5432123412345678, 8),
-                       0x0010: (0xabcdef0187654321, 8),
-                       0x0040: (0x1828384822324252, 8),
+                       0x0008: (0xabcdef0187654321, 8),
+                       0x0020: (0x1828384822324252, 8),
                         }
-        self.run_tst_program(Program(lst), initial_regs,
+        self.run_tst_program(Program(lst, bigendian), initial_regs,
                              initial_mem=initial_mem)
 
     def test_3_load_store(self):
@@ -98,9 +99,83 @@ class LDSTTestCase(FHDLTestCase):
         initial_regs[2] = 0x0002
         initial_regs[3] = 0x15eb
         initial_mem = {0x0000: (0x5432123412345678, 8),
-                       0x0010: (0xabcdef0187654321, 8),
-                       0x0040: (0x1828384822324252, 8),
+                       0x0008: (0xabcdef0187654321, 8),
+                       0x0020: (0x1828384822324252, 8),
                         }
-        self.run_tst_program(Program(lst), initial_regs,
+        self.run_tst_program(Program(lst, bigendian), initial_regs,
+                             initial_mem=initial_mem)
+
+    def test_4_load_store_rev_ext(self):
+        lst = ["stwx 1, 4, 2",
+               "lwbrx 3, 4, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x5678
+        initial_regs[2] = 0x001c
+        initial_regs[4] = 0x0008
+        initial_mem = {0x0000: (0x5432123412345678, 8),
+                       0x0008: (0xabcdef0187654321, 8),
+                       0x0020: (0x1828384822324252, 8),
+                        }
+        self.run_tst_program(Program(lst, bigendian), initial_regs,
+                             initial_mem=initial_mem)
+
+    def test_5_load_store_rev_ext(self):
+        lst = ["stwbrx 1, 4, 2",
+               "lwzx 3, 4, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x5678
+        initial_regs[2] = 0x001c
+        initial_regs[4] = 0x0008
+        initial_mem = {0x0000: (0x5432123412345678, 8),
+                       0x0008: (0xabcdef0187654321, 8),
+                       0x0020: (0x1828384822324252, 8),
+                        }
+        self.run_tst_program(Program(lst, bigendian), initial_regs,
+                             initial_mem=initial_mem)
+
+    def test_6_load_store_rev_ext(self):
+        lst = ["stwbrx 1, 4, 2",
+               "lwbrx 3, 4, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x5678
+        initial_regs[2] = 0x001c
+        initial_regs[4] = 0x0008
+        initial_mem = {0x0000: (0x5432123412345678, 8),
+                       0x0008: (0xabcdef0187654321, 8),
+                       0x0020: (0x1828384822324252, 8),
+                        }
+        self.run_tst_program(Program(lst, bigendian), initial_regs,
+                             initial_mem=initial_mem)
+
+    def test_7_load_store_d(self):
+        lst = [
+               "std 3, 0(2)",
+               "ld 4, 0(2)",
+        ]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x0004
+        initial_regs[2] = 0x0008
+        initial_regs[3] = 0x00ee
+        initial_mem = {0x0000: (0x5432123412345678, 8),
+                       0x0008: (0xabcdef0187654321, 8),
+                       0x0020: (0x1828384822324252, 8),
+                        }
+        self.run_tst_program(Program(lst, bigendian), initial_regs,
+                             initial_mem=initial_mem)
+
+    def test_8_load_store_d_update(self):
+        lst = [
+               "stdu 3, 0(2)",
+               "ld 4, 0(2)",
+        ]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x0004
+        initial_regs[2] = 0x0008
+        initial_regs[3] = 0x00ee
+        initial_mem = {0x0000: (0x5432123412345678, 8),
+                       0x0008: (0xabcdef0187654321, 8),
+                       0x0020: (0x1828384822324252, 8),
+                        }
+        self.run_tst_program(Program(lst, bigendian), initial_regs,
                              initial_mem=initial_mem)