rename InternalOp to MicrOp

[soc.git] / src / soc / fu / logical / formal / proof_input_stage.py

diff --git a/src/soc/fu/logical/formal/proof_input_stage.py b/src/soc/fu/logical/formal/proof_input_stage.py
index 16f3df0432413d6eb963db6d945c88eb537368d2..ab6e392e75061862365c331d05acecb84d7b5406 100644 (file)
--- a/src/soc/fu/logical/formal/proof_input_stage.py
+++ b/src/soc/fu/logical/formal/proof_input_stage.py
@@ -9,7 +9,7 @@ from nmigen.cli import rtlil
 from soc.fu.alu.input_stage import ALUInputStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
 import unittest
 
 
@@ -57,7 +57,7 @@ class Driver(Elaboratable):
             comb += Assert(dut.o.a == a)
 
         with m.If(rec.imm_data.imm_ok &
-                  ~(rec.insn_type == InternalOp.OP_RLC)):
+                  ~(rec.insn_type == MicrOp.OP_RLC)):
             comb += Assert(dut.o.b == rec.imm_data.imm)
         with m.Else():
             comb += Assert(dut.o.b == b)