move over to from openpower imports

[soc.git] / src / soc / fu / logical / formal / proof_input_stage.py

diff --git a/src/soc/fu/logical/formal/proof_input_stage.py b/src/soc/fu/logical/formal/proof_input_stage.py
index ed0c75119326f54c553b16c627e753f229a9e7ea..d11f832df0b7e4d68957e85c40e83ca013b5aaf8 100644 (file)
--- a/src/soc/fu/logical/formal/proof_input_stage.py
+++ b/src/soc/fu/logical/formal/proof_input_stage.py
@@ -9,7 +9,7 @@ from nmigen.cli import rtlil
 from soc.fu.alu.input_stage import ALUInputStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
 import unittest