add logical compunit test

[soc.git] / src / soc / fu / logical / logical_input_record.py

diff --git a/src/soc/fu/logical/logical_input_record.py b/src/soc/fu/logical/logical_input_record.py
index c6641a0145f2ec29d61bce923aa24e82b1a9d17a..34d1dd917bc26749fb7c3112ae367b0057d38558 100644 (file)
--- a/src/soc/fu/logical/logical_input_record.py
+++ b/src/soc/fu/logical/logical_input_record.py
@@ -21,6 +21,7 @@ class CompLogicalOpSubset(Record):
                   ('zero_a', 1),
                   ('input_carry', CryIn),
                   ('invert_out', 1),
+                  ('write_cr', Layout((("data", 3), ("ok", 1)))), # Data
                   ('output_carry', 1),
                   ('is_32bit', 1),
                   ('is_signed', 1),