convert to individual PipeSpecs for each pipeline

[soc.git] / src / soc / fu / logical / pipe_data.py

diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index 9ed7252f4c36715b0f061c83e575086bfeb482d9..256317cb62012c90ba4b865b1545786b872ca17b 100644 (file)
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -1,6 +1,8 @@
 from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.alu.pipe_data import IntegerData
+from soc.fu.alu.pipe_data import IntegerData, ALUOutputData
+from nmutil.dynamicpipe import SimpleHandshakeRedir
+from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
 
 
 class LogicalInputData(IntegerData):
@@ -27,3 +29,15 @@ class LogicalInputData(IntegerData):
         return lst + [self.a.eq(i.a), self.b.eq(i.b),
                       self.xer_ca.eq(i.xer_ca),
                       self.xer_so.eq(i.xer_so)]
+
+
+# TODO: replace CompALUOpSubset with CompLogicalOpSubset
+class LogicalPipeSpec:
+    regspec = (LogicalInputData.regspec, ALUOutputData.regspec)
+    opsubsetkls = CompALUOpSubset
+    def __init__(self, id_wid, op_wid):
+        self.id_wid = id_wid
+        self.op_wid = op_wid
+        self.opkls = lambda _: self.opsubsetkls(name="op")
+        self.stage = None
+        self.pipekls = SimpleHandshakeRedir