normalise XER regs carry/32 and SO

[soc.git] / src / soc / fu / logical / test / test_pipe_caller.py

diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index 79c1e291b6d8ec1fa55d99ef82f8777832978c13..4a22308c071ef86cde9bfd8f2e3b5a1d4b348f48 100644 (file)
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -12,9 +12,9 @@ from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 
 
-from soc.logical.pipeline import LogicalBasePipe
-from soc.alu.alu_input_record import CompALUOpSubset
-from soc.alu.pipe_data import ALUPipeSpec
+from soc.fu.logical.pipeline import LogicalBasePipe
+from soc.fu.alu.alu_input_record import CompALUOpSubset
+from soc.fu.alu.pipe_data import ALUPipeSpec
 import random
 
 
@@ -68,9 +68,11 @@ def set_alu_inputs(alu, dec2, sim):
 
 def set_extra_alu_inputs(alu, dec2, sim):
     carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
-    yield alu.p.data_i.carry_in.eq(carry)
+    carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
+    yield alu.p.data_i.xer_ca[0].eq(carry)
+    yield alu.p.data_i.xer_ca[1].eq(carry32)
     so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
-    yield alu.p.data_i.so.eq(so)
+    yield alu.p.data_i.xer_so.eq(so)
     
 
 # This test bench is a bit different than is usual. Initially when I
@@ -123,10 +125,9 @@ class LogicalTestCase(FHDLTestCase):
             initial_regs[1] = random.randint(0, (1<<64)-1)
             self.run_tst_program(Program(lst), initial_regs)
 
-    @unittest.skip("broken")
     def test_cntz(self):
-        insns = ["cntlzd", "cnttzd"]
-        for i in range(10):
+        insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"]
+        for i in range(100):
             choice = random.choice(insns)
             lst = [f"{choice} 3, 1"]
             print(lst)
@@ -154,6 +155,14 @@ class LogicalTestCase(FHDLTestCase):
             initial_regs[1] = random.randint(0, (1<<64)-1)
             self.run_tst_program(Program(lst), initial_regs)
 
+    def test_popcnt_edge(self):
+        insns = ["popcntb", "popcntw", "popcntd"]
+        for choice in insns:
+            lst = [f"{choice} 3, 1"]
+            initial_regs = [0] * 32
+            initial_regs[1] = -1
+            self.run_tst_program(Program(lst), initial_regs)
+
     def test_cmpb(self):
         lst = ["cmpb 3, 1, 2"]
         initial_regs = [0] * 32
@@ -239,18 +248,18 @@ class TestRunner(FHDLTestCase):
                         print(f"expected {expected:x}, actual: {alu_out:x}")
                         self.assertEqual(expected, alu_out, code)
                     yield from self.check_extra_alu_outputs(alu, pdecode2,
-                                                            simulator)
+                                                            simulator, code)
 
         sim.add_sync_process(process)
         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
                             traces=[]):
             sim.run()
-    def check_extra_alu_outputs(self, alu, dec2, sim):
+    def check_extra_alu_outputs(self, alu, dec2, sim, code):
         rc = yield dec2.e.rc.data
         if rc:
             cr_expected = sim.crl[0].get_range().value
-            cr_actual = yield alu.n.data_o.cr0
-            self.assertEqual(cr_expected, cr_actual)
+            cr_actual = yield alu.n.data_o.cr0.data
+            self.assertEqual(cr_expected, cr_actual, code)
 
 
 if __name__ == "__main__":