from nmigen import Module, Signal
from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
import unittest
from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
+from soc.config.endian import bigendian
+from soc.fu.test.common import TestAccumulatorBase, TestCase, ALUHelpers
from soc.fu.logical.pipeline import LogicalBasePipe
-from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.fu.alu.pipe_data import ALUPipeSpec
+from soc.fu.logical.pipe_data import LogicalPipeSpec
import random
-class TestCase:
- def __init__(self, program, regs, sprs, name):
- self.program = program
- self.regs = regs
- self.sprs = sprs
- self.name = name
+def get_cu_inputs(dec2, sim):
+ """naming (res) must conform to LogicalFunctionUnit input regspec
+ """
+ res = {}
+ yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
+ yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
-def get_rec_width(rec):
- recwidth = 0
- # Setup random inputs for dut.op
- for p in rec.ports():
- width = p.width
- recwidth += width
- return recwidth
+ return res
def set_alu_inputs(alu, dec2, sim):
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
# and place it into data_i.b
- reg3_ok = yield dec2.e.read_reg3.ok
- reg1_ok = yield dec2.e.read_reg1.ok
- assert reg3_ok != reg1_ok
- if reg3_ok:
- data1 = yield dec2.e.read_reg3.data
- data1 = sim.gpr(data1).value
- elif reg1_ok:
- data1 = yield dec2.e.read_reg1.data
- data1 = sim.gpr(data1).value
- else:
- data1 = 0
-
- yield alu.p.data_i.a.eq(data1)
-
- # If there's an immediate, set the B operand to that
- reg2_ok = yield dec2.e.read_reg2.ok
- imm_ok = yield dec2.e.imm_data.imm_ok
- if imm_ok:
- data2 = yield dec2.e.imm_data.imm
- elif reg2_ok:
- data2 = yield dec2.e.read_reg2.data
- data2 = sim.gpr(data2).value
- else:
- data2 = 0
- yield alu.p.data_i.b.eq(data2)
-
-
-def set_extra_alu_inputs(alu, dec2, sim):
- carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
- carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
- yield alu.p.data_i.xer_ca[0].eq(carry)
- yield alu.p.data_i.xer_ca[1].eq(carry32)
- so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
- yield alu.p.data_i.xer_so.eq(so)
+ inp = yield from get_cu_inputs(dec2, sim)
+ yield from ALUHelpers.set_int_ra(alu, dec2, inp)
+ yield from ALUHelpers.set_int_rb(alu, dec2, inp)
# This test bench is a bit different than is usual. Initially when I
# massively. Before, it took around 1 minute on my computer, now it
# takes around 3 seconds
-test_data = []
+class LogicalTestCase(TestAccumulatorBase):
-class LogicalTestCase(FHDLTestCase):
- def __init__(self, name):
- super().__init__(name)
- self.test_name = name
-
- def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
- tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
- test_data.append(tc)
+ def case_complement(self):
+ insns = ["andc", "orc"]
+ for i in range(40):
+ choice = random.choice(insns)
+ lst = [f"{choice} 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = random.randint(0, (1 << 64)-1)
+ initial_regs[2] = random.randint(0, (1 << 64)-1)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_rand(self):
+ def case_rand(self):
insns = ["and", "or", "xor"]
for i in range(40):
choice = random.choice(insns)
initial_regs = [0] * 32
initial_regs[1] = random.randint(0, (1 << 64)-1)
initial_regs[2] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_rand_imm_logical(self):
+ def case_rand_imm_logical(self):
insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
for i in range(10):
choice = random.choice(insns)
print(lst)
initial_regs = [0] * 32
initial_regs[1] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_cntz(self):
+ def case_cntz(self):
insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"]
for i in range(100):
choice = random.choice(insns)
print(lst)
initial_regs = [0] * 32
initial_regs[1] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_parity(self):
+ def case_parity(self):
insns = ["prtyw", "prtyd"]
for i in range(10):
choice = random.choice(insns)
print(lst)
initial_regs = [0] * 32
initial_regs[1] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_popcnt(self):
+ def case_popcnt(self):
insns = ["popcntb", "popcntw", "popcntd"]
for i in range(10):
choice = random.choice(insns)
print(lst)
initial_regs = [0] * 32
initial_regs[1] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_popcnt_edge(self):
+ def case_popcnt_edge(self):
insns = ["popcntb", "popcntw", "popcntd"]
for choice in insns:
lst = [f"{choice} 3, 1"]
initial_regs = [0] * 32
initial_regs[1] = -1
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_cmpb(self):
+ def case_cmpb(self):
lst = ["cmpb 3, 1, 2"]
initial_regs = [0] * 32
initial_regs[1] = 0xdeadbeefcafec0de
initial_regs[2] = 0xd0adb0000afec1de
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_bpermd(self):
+ def case_bpermd(self):
lst = ["bpermd 3, 1, 2"]
for i in range(20):
initial_regs = [0] * 32
- initial_regs[1] = 1<<random.randint(0,63)
+ initial_regs[1] = 1 << random.randint(0, 63)
initial_regs[2] = 0xdeadbeefcafec0de
- self.run_tst_program(Program(lst), initial_regs)
-
- def test_ilang(self):
- rec = CompALUOpSubset()
+ self.add_case(Program(lst, bigendian), initial_regs)
- pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ def case_ilang(self):
+ pspec = LogicalPipeSpec(id_wid=2)
alu = LogicalBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("logical_pipeline.il", "w") as f:
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- rec = CompALUOpSubset()
-
- pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = LogicalPipeSpec(id_wid=2)
m.submodules.alu = alu = LogicalBasePipe(pspec)
comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
- comb += alu.p.valid_i.eq(1)
comb += alu.n.ready_i.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
print(test.name)
program = test.program
self.subTest(test.name)
- simulator = ISA(pdecode2, test.regs, test.sprs, 0)
+ simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
+ test.mem, test.msr,
+ bigendian=bigendian)
gen = program.generate_instructions()
instructions = list(zip(gen, program.assembly.splitlines()))
print(code)
# ask the decoder to decode this binary data (endian'd)
- yield pdecode2.dec.bigendian.eq(0) # little / big?
+ yield pdecode2.dec.bigendian.eq(bigendian) # little / big?
yield instruction.eq(ins) # raw binary instr.
yield Settle()
- fn_unit = yield pdecode2.e.fn_unit
+ fn_unit = yield pdecode2.e.do.fn_unit
self.assertEqual(fn_unit, Function.LOGICAL.value, code)
yield from set_alu_inputs(alu, pdecode2, simulator)
- yield from set_extra_alu_inputs(alu, pdecode2, simulator)
+
+ # set valid for one cycle, propagate through pipeline...
+ yield alu.p.valid_i.eq(1)
yield
+ yield alu.p.valid_i.eq(0)
+
opname = code.split(' ')[0]
yield from simulator.call(opname)
index = simulator.pc.CIA.value//4
yield
vld = yield alu.n.valid_o
yield
- alu_out = yield alu.n.data_o.o
- out_reg_valid = yield pdecode2.e.write_reg.ok
- if out_reg_valid:
- write_reg_idx = yield pdecode2.e.write_reg.data
- expected = simulator.gpr(write_reg_idx).value
- print(f"expected {expected:x}, actual: {alu_out:x}")
- self.assertEqual(expected, alu_out, code)
- yield from self.check_extra_alu_outputs(alu, pdecode2,
- simulator, code)
+
+ yield from self.check_alu_outputs(alu, pdecode2,
+ simulator, code)
+ yield Settle()
+
sim.add_sync_process(process)
- with sim.write_vcd("simulator.vcd", "simulator.gtkw",
+ with sim.write_vcd("logical_simulator.vcd", "logical_simulator.gtkw",
traces=[]):
sim.run()
- def check_extra_alu_outputs(self, alu, dec2, sim, code):
- rc = yield dec2.e.rc.data
+ def check_alu_outputs(self, alu, dec2, sim, code):
+
+ rc = yield dec2.e.do.rc.data
+ cridx_ok = yield dec2.e.write_cr.ok
+ cridx = yield dec2.e.write_cr.data
+
+ print("check extra output", repr(code), cridx_ok, cridx)
if rc:
- cr_expected = sim.crl[0].get_range().value
- cr_actual = yield alu.n.data_o.cr0.data
- self.assertEqual(cr_expected, cr_actual, code)
+ self.assertEqual(cridx, 0, code)
+
+ sim_o = {}
+ res = {}
+
+ yield from ALUHelpers.get_cr_a(res, alu, dec2)
+ yield from ALUHelpers.get_int_o(res, alu, dec2)
+
+ yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
+ yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
+
+ ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
+ ALUHelpers.check_int_o(self, res, sim_o, code)
if __name__ == "__main__":
unittest.main(exit=False)
suite = unittest.TestSuite()
- suite.addTest(TestRunner(test_data))
+ suite.addTest(TestRunner(LogicalTestCase().test_data))
runner = unittest.TextTestRunner()
runner.run(suite)
projects / soc.git / blobdiff