from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
+from soc.config.endian import bigendian
-from soc.fu.test.common import TestCase, ALUHelpers
+
+from soc.fu.test.common import TestAccumulatorBase, TestCase, ALUHelpers
from soc.fu.logical.pipeline import LogicalBasePipe
from soc.fu.logical.pipe_data import LogicalPipeSpec
import random
"""
res = {}
- yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
- yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
+ yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
+ yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
return res
# takes around 3 seconds
-class LogicalTestCase(FHDLTestCase):
- test_data = []
- def __init__(self, name):
- super().__init__(name)
- self.test_name = name
+class LogicalTestCase(TestAccumulatorBase):
- def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
- tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
- self.test_data.append(tc)
+ def case_complement(self):
+ insns = ["andc", "orc"]
+ for i in range(40):
+ choice = random.choice(insns)
+ lst = [f"{choice} 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = random.randint(0, (1 << 64)-1)
+ initial_regs[2] = random.randint(0, (1 << 64)-1)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_rand(self):
+ def case_rand(self):
insns = ["and", "or", "xor"]
for i in range(40):
choice = random.choice(insns)
initial_regs = [0] * 32
initial_regs[1] = random.randint(0, (1 << 64)-1)
initial_regs[2] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_rand_imm_logical(self):
+ def case_rand_imm_logical(self):
insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
for i in range(10):
choice = random.choice(insns)
print(lst)
initial_regs = [0] * 32
initial_regs[1] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_cntz(self):
+ def case_cntz(self):
insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"]
for i in range(100):
choice = random.choice(insns)
print(lst)
initial_regs = [0] * 32
initial_regs[1] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_parity(self):
+ def case_parity(self):
insns = ["prtyw", "prtyd"]
for i in range(10):
choice = random.choice(insns)
print(lst)
initial_regs = [0] * 32
initial_regs[1] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_popcnt(self):
+ def case_popcnt(self):
insns = ["popcntb", "popcntw", "popcntd"]
for i in range(10):
choice = random.choice(insns)
print(lst)
initial_regs = [0] * 32
initial_regs[1] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_popcnt_edge(self):
+ def case_popcnt_edge(self):
insns = ["popcntb", "popcntw", "popcntd"]
for choice in insns:
lst = [f"{choice} 3, 1"]
initial_regs = [0] * 32
initial_regs[1] = -1
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_cmpb(self):
+ def case_cmpb(self):
lst = ["cmpb 3, 1, 2"]
initial_regs = [0] * 32
initial_regs[1] = 0xdeadbeefcafec0de
initial_regs[2] = 0xd0adb0000afec1de
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_bpermd(self):
+ def case_bpermd(self):
lst = ["bpermd 3, 1, 2"]
for i in range(20):
initial_regs = [0] * 32
- initial_regs[1] = 1<<random.randint(0,63)
+ initial_regs[1] = 1 << random.randint(0, 63)
initial_regs[2] = 0xdeadbeefcafec0de
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_ilang(self):
+ def case_ilang(self):
pspec = LogicalPipeSpec(id_wid=2)
alu = LogicalBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
m.submodules.alu = alu = LogicalBasePipe(pspec)
comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
- comb += alu.p.valid_i.eq(1)
comb += alu.n.ready_i.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
program = test.program
self.subTest(test.name)
simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
- test.mem, test.msr)
+ test.mem, test.msr,
+ bigendian=bigendian)
gen = program.generate_instructions()
instructions = list(zip(gen, program.assembly.splitlines()))
print(code)
# ask the decoder to decode this binary data (endian'd)
- yield pdecode2.dec.bigendian.eq(0) # little / big?
+ yield pdecode2.dec.bigendian.eq(bigendian) # little / big?
yield instruction.eq(ins) # raw binary instr.
yield Settle()
- fn_unit = yield pdecode2.e.fn_unit
+ fn_unit = yield pdecode2.e.do.fn_unit
self.assertEqual(fn_unit, Function.LOGICAL.value, code)
yield from set_alu_inputs(alu, pdecode2, simulator)
+
+ # set valid for one cycle, propagate through pipeline...
+ yield alu.p.valid_i.eq(1)
yield
+ yield alu.p.valid_i.eq(0)
+
opname = code.split(' ')[0]
yield from simulator.call(opname)
index = simulator.pc.CIA.value//4
yield from self.check_alu_outputs(alu, pdecode2,
simulator, code)
+ yield Settle()
+
sim.add_sync_process(process)
with sim.write_vcd("logical_simulator.vcd", "logical_simulator.gtkw",
def check_alu_outputs(self, alu, dec2, sim, code):
- rc = yield dec2.e.rc.data
+ rc = yield dec2.e.do.rc.data
cridx_ok = yield dec2.e.write_cr.ok
cridx = yield dec2.e.write_cr.data
- print ("check extra output", repr(code), cridx_ok, cridx)
+ print("check extra output", repr(code), cridx_ok, cridx)
if rc:
self.assertEqual(cridx, 0, code)
yield from ALUHelpers.get_int_o(res, alu, dec2)
yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
- yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2)
+ yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
ALUHelpers.check_int_o(self, res, sim_o, code)
if __name__ == "__main__":
unittest.main(exit=False)
suite = unittest.TestSuite()
- suite.addTest(TestRunner(LogicalTestCase.test_data))
+ suite.addTest(TestRunner(LogicalTestCase().test_data))
runner = unittest.TextTestRunner()
runner.run(suite)
projects / soc.git / blobdiff