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[soc.git] / src / soc / fu / mul / pipe_data.py

diff --git a/src/soc/fu/mul/pipe_data.py b/src/soc/fu/mul/pipe_data.py
index 38741f61bab416c2d2bd10388aa58b47280a7424..bb77c5ce2988ddad420006b3005b6548cefc2978 100644 (file)
--- a/src/soc/fu/mul/pipe_data.py
+++ b/src/soc/fu/mul/pipe_data.py
@@ -1,10 +1,10 @@
 from soc.fu.mul.mul_input_record import CompMULOpSubset
 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from soc.fu.alu.pipe_data import ALUOutputData, ALUInputData
+from soc.fu.div.pipe_data import DivInputData, DivMulOutputData
 from nmigen import Signal
 
 
-class MulIntermediateData(ALUInputData):
+class MulIntermediateData(DivInputData):
     def __init__(self, pspec):
         super().__init__(pspec)
 
@@ -16,8 +16,7 @@ class MulIntermediateData(ALUInputData):
 
 class MulOutputData(IntegerData):
     regspec = [('INT', 'o', '0:128'),
-               ('XER', 'xer_so', '32'), # XER bit 32: SO
-               ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
+               ('XER', 'xer_so', '32')] # XER bit 32: SO
     def __init__(self, pspec):
         super().__init__(pspec, False) # still input style
 
@@ -28,5 +27,5 @@ class MulOutputData(IntegerData):
 
 
 class MulPipeSpec(CommonPipeSpec):
-    regspec = (ALUInputData.regspec, ALUOutputData.regspec)
+    regspec = (DivInputData.regspec, DivMulOutputData.regspec)
     opsubsetkls = CompMULOpSubset