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[soc.git] / src / soc / fu / mul / pipe_data.py

diff --git a/src/soc/fu/mul/pipe_data.py b/src/soc/fu/mul/pipe_data.py
index 495d503b4ff1bffffb02e251b19cb64a2c92dd80..bb77c5ce2988ddad420006b3005b6548cefc2978 100644 (file)
--- a/src/soc/fu/mul/pipe_data.py
+++ b/src/soc/fu/mul/pipe_data.py
@@ -1,10 +1,31 @@
-from soc.fu.alu.alu_input_record import CompALUOpSubset
+from soc.fu.mul.mul_input_record import CompMULOpSubset
 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from soc.fu.alu.pipe_data import ALUOutputData
-from soc.fu.shift_rot.pipe_data import ShoftRotInputData
+from soc.fu.div.pipe_data import DivInputData, DivMulOutputData
+from nmigen import Signal
 
 
-# TODO: replace CompALUOpSubset with CompShiftRotOpSubset
-class ShiftRotPipeSpec(CommonPipeSpec):
-    regspec = (ShiftRotInputData.regspec, ALUOutputData.regspec)
-    opsubsetkls = CompALUOpSubset
+class MulIntermediateData(DivInputData):
+    def __init__(self, pspec):
+        super().__init__(pspec)
+
+        self.neg_res = Signal(reset_less=True)
+        self.neg_res32 = Signal(reset_less=True)
+        self.data.append(self.neg_res)
+        self.data.append(self.neg_res32)
+
+
+class MulOutputData(IntegerData):
+    regspec = [('INT', 'o', '0:128'),
+               ('XER', 'xer_so', '32')] # XER bit 32: SO
+    def __init__(self, pspec):
+        super().__init__(pspec, False) # still input style
+
+        self.neg_res = Signal(reset_less=True)
+        self.neg_res32 = Signal(reset_less=True)
+        self.data.append(self.neg_res)
+        self.data.append(self.neg_res32)
+
+
+class MulPipeSpec(CommonPipeSpec):
+    regspec = (DivInputData.regspec, DivMulOutputData.regspec)
+    opsubsetkls = CompMULOpSubset