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[soc.git] / src / soc / fu / mul / post_stage.py

diff --git a/src/soc/fu/mul/post_stage.py b/src/soc/fu/mul/post_stage.py
index 1c144ad1c85281170231003a48b721a2a7b10950..14d2d91114f5e8b318028bde087c38896da55be2 100644 (file)
--- a/src/soc/fu/mul/post_stage.py
+++ b/src/soc/fu/mul/post_stage.py
@@ -39,29 +39,35 @@ class MulMainStage3(PipeModBase):
         # check negate: select signed/unsigned
         mul_o = Signal(o_i.width, reset_less=True)
         comb += mul_o.eq(Mux(self.i.neg_res, -o_i, o_i))
-        comb += o.ok.eq(1)
 
         # OP_MUL_nnn - select hi32/hi64/lo64 from result
         with m.Switch(op.insn_type):
             # hi-32 replicated twice
             with m.Case(MicrOp.OP_MUL_H32):
                 comb += o.data.eq(Repl(mul_o[32:64], 2))
+                comb += o.ok.eq(1)
             # hi-64 
             with m.Case(MicrOp.OP_MUL_H64):
                 comb += o.data.eq(mul_o[64:128])
+                comb += o.ok.eq(1)
             # lo-64 - overflow
-            with m.Default():
+            with m.Case(MicrOp.OP_MUL_L64):
                 # take the low 64 bits of the mul
                 comb += o.data.eq(mul_o[0:64])
+                comb += o.ok.eq(1)
 
-                # compute overflow
+                # compute overflow 32/64
                 mul_ov = Signal(reset_less=True)
                 with m.If(is_32bit):
-                    m32 = mul_o[31:64] # yes really bits 31 to 63 (incl)
-                    comb += mul_ov.eq(m32.bool() & ~m32.all())
+                    # here we're checking that the top 32 bits is the
+                    # sign-extended version of the bottom 32 bits.
+                    m31 = mul_o[31:64] # yes really bits 31 to 63 (incl)
+                    comb += mul_ov.eq(m31.bool() & ~m31.all())
                 with m.Else():
-                    m64 = mul_o[63:128] # yes really bits 63 to 127 (incl)
-                    comb += mul_ov.eq(m64.bool() & ~m64.all())
+                    # here we're checking that the top 64 bits is the
+                    # sign-extended version of the bottom 64 bits.
+                    m63 = mul_o[63:128] # yes really bits 63 to 127 (incl)
+                    comb += mul_ov.eq(m63.bool() & ~m63.all())
 
                 # 32-bit (ov[1]) and 64-bit (ov[0]) overflow - both same
                 comb += ov_o.data.eq(Repl(mul_ov, 2)) # sets OV _and_ OV32
@@ -69,7 +75,7 @@ class MulMainStage3(PipeModBase):
 
         ###### sticky overflow and context, both pass-through #####
 
-        comb += self.o.xer_so.data.eq(self.i.xer_so)
+        comb += self.o.xer_so.eq(self.i.xer_so)
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m