from nmigen import (Module, Signal, Mux)
from nmutil.pipemodbase import PipeModBase
-from soc.fu.alu.pipe_data import ALUInputData
+from soc.fu.div.pipe_data import DivInputData
from soc.fu.mul.pipe_data import MulIntermediateData
from ieee754.part.partsig import PartitionedSignal
from nmutil.util import eq32
super().__init__(pspec, "mul1")
def ispec(self):
- return ALUInputData(self.pspec) # defines pipeline stage input format
+ return DivInputData(self.pspec) # defines pipeline stage input format
def ospec(self):
return MulIntermediateData(self.pspec) # pipeline stage output format
###### XER and context, both pass-through #####
- comb += self.o.xer_ca.eq(self.i.xer_ca)
comb += self.o.xer_so.eq(self.i.xer_so)
comb += self.o.ctx.eq(self.i.ctx)