missing conversion of DIV to Div

[soc.git] / src / soc / fu / mul / pre_stage.py

diff --git a/src/soc/fu/mul/pre_stage.py b/src/soc/fu/mul/pre_stage.py
index 94563874881c5b804b5b0c93a60785f98808b3a4..f22964dd5b50be0930fe6fa77c1841486b1363e1 100644 (file)
--- a/src/soc/fu/mul/pre_stage.py
+++ b/src/soc/fu/mul/pre_stage.py
@@ -2,7 +2,7 @@
 
 from nmigen import (Module, Signal, Mux)
 from nmutil.pipemodbase import PipeModBase
-from soc.fu.div.pipe_data import DIVInputData
+from soc.fu.div.pipe_data import DivInputData
 from soc.fu.mul.pipe_data import MulIntermediateData
 from ieee754.part.partsig import PartitionedSignal
 from nmutil.util import eq32
@@ -12,7 +12,7 @@ class MulMainStage1(PipeModBase):
         super().__init__(pspec, "mul1")
 
     def ispec(self):
-        return DIVInputData(self.pspec) # defines pipeline stage input format
+        return DivInputData(self.pspec) # defines pipeline stage input format
 
     def ospec(self):
         return MulIntermediateData(self.pspec) # pipeline stage output format