add link to rotator, sign-extend mode OP_EXTSWSLI

[soc.git] / src / soc / fu / regspec.py

diff --git a/src/soc/fu/regspec.py b/src/soc/fu/regspec.py
index 0aa2842c173be5ec1daade1ef170a9014ede32e9..1524e8aa3dbf05340d45168fca9182e9d0cae087 100644 (file)
--- a/src/soc/fu/regspec.py
+++ b/src/soc/fu/regspec.py
@@ -17,6 +17,8 @@ which MultiCompUnit port, how wide the connection is, and so on.
 
 """
 from nmigen import Const
+from soc.regfile.regfiles import XERRegs, FastRegs
+
 
 def get_regspec_bitwidth(regspec, srcdest, idx):
     print ("get_regspec_bitwidth", regspec, srcdest, idx)
@@ -55,21 +57,36 @@ class RegSpec:
         return get_regspec_bitwidth(self._rwid, 0, i)
 
 
-class RegSpecALUAPI:
-    def __init__(self, rwid, alu):
+class RegSpecAPI:
+    def __init__(self, rwid):
         """RegSpecAPI
 
         * :rwid:       regspec
-        * :alu:        ALU covered by this regspec
         """
         self.rwid = rwid
-        self.alu = alu # actual ALU - set as a "submodule" of the CU
+
+    def get_in_spec(self, i):
+        return self.rwid[0][i]
+
+    def get_out_spec(self, i):
+        return self.rwid[1][i]
 
     def get_in_name(self, i):
-        return self.rwid[0][i][1]
+        return self.get_in_spec(i)[1]
 
     def get_out_name(self, i):
-        return self.rwid[1][i][1]
+        return self.get_out_spec(i)[1]
+
+
+class RegSpecALUAPI(RegSpecAPI):
+    def __init__(self, rwid, alu):
+        """RegSpecAPI
+
+        * :rwid:       regspec
+        * :alu:        ALU covered by this regspec
+        """
+        super().__init__(rwid)
+        self.alu = alu
 
     def get_out(self, i):
         if isinstance(self.rwid, int): # old - testing - API (rwid is int)
@@ -87,31 +104,3 @@ class RegSpecALUAPI:
         if isinstance(self.rwid, int): # old - testing - API (rwid is int)
             return self.alu.op
         return self.alu.p.data_i.ctx.op
-
-
-# function for the relationship between regspecs and Decode2Execute1Type
-def regspec_rdmask(e, regspec, idx):
-    (regfile, name, _) = regspec[idx]
-    if regfile == 'INT':
-        if name == 'ra': # RA
-            return e.read_reg1.ok
-        if name == 'rb': # RB
-            return e.read_reg2.ok
-        if name == 'rc': # RS
-            return e.read_reg3.ok
-    if regfile == 'CR':
-        if name == 'full_cr': # full CR
-            return e.read_cr_whole
-        if name == 'cr_a': # CR A
-            return e.read_cr1.ok
-        if name == 'cr_b': # CR B
-            return e.read_cr2.ok
-        if name == 'cr_c': # CR C
-            return e.read_cr3.ok
-    if regfile == 'XER':
-        if name in ['xer_so', 'xer_ov']:
-            return e.oe.oe & e.oe.oe_ok
-        if name == 'xer_ca':
-            return e.input_carry
-
-    assert False, "regspec rdmask not found %s %d" % (repr(regspec), idx)