check problem state in OP_MTMSRD from original reg RA rather than

[soc.git] / src / soc / fu / regspec.py

diff --git a/src/soc/fu/regspec.py b/src/soc/fu/regspec.py
index 07d071206f5e65d8ca41040cb1a59f7c96812b32..6804c593971fab5adcce20ddccaf797439a65e86 100644 (file)
--- a/src/soc/fu/regspec.py
+++ b/src/soc/fu/regspec.py
@@ -65,6 +65,11 @@ class RegSpecAPI:
         """
         self.rwid = rwid
 
+    def get_io_spec(self, direction, i):
+        if direction: # input (read specs)
+            return self.get_in_spec(i)
+        return self.get_out_spec(i)
+
     def get_in_spec(self, i):
         return self.rwid[0][i]
 
@@ -92,15 +97,15 @@ class RegSpecALUAPI(RegSpecAPI):
         if isinstance(self.rwid, int):  # old - testing - API (rwid is int)
             return self.alu.out[i]
         # regspec-based API: look up variable through regspec thru row number
-        return getattr(self.alu.n.data_o, self.get_out_name(i))
+        return getattr(self.alu.n.o_data, self.get_out_name(i))
 
     def get_in(self, i):
         if isinstance(self.rwid, int):  # old - testing - API (rwid is int)
             return self.alu.i[i]
         # regspec-based API: look up variable through regspec thru row number
-        return getattr(self.alu.p.data_i, self.get_in_name(i))
+        return getattr(self.alu.p.i_data, self.get_in_name(i))
 
     def get_op(self):
         if isinstance(self.rwid, int):  # old - testing - API (rwid is int)
             return self.alu.op
-        return self.alu.p.data_i.ctx.op
+        return self.alu.p.i_data.ctx.op