extra check on rd.req in test_alu_compunit

[soc.git] / src / soc / fu / regspec.py

diff --git a/src/soc/fu/regspec.py b/src/soc/fu/regspec.py
index 009f1fbc5e63caa579f3fbf3337f54941760c7df..e7a4cf8e3d88936f0aba3c6b550a943aaab1d692 100644 (file)
--- a/src/soc/fu/regspec.py
+++ b/src/soc/fu/regspec.py
@@ -19,6 +19,7 @@ which MultiCompUnit port, how wide the connection is, and so on.
 
 
 def get_regspec_bitwidth(regspec, srcdest, idx):
+    print ("get_regspec_bitwidth", regspec, srcdest, idx)
     bitspec = regspec[srcdest][idx]
     wid = 0
     print (bitspec)