extra check on rd.req in test_alu_compunit

[soc.git] / src / soc / fu / regspec.py

diff --git a/src/soc/fu/regspec.py b/src/soc/fu/regspec.py
index 4e6fc5d1ce3cd9b2ad94cf26f4dae29db57c658a..e7a4cf8e3d88936f0aba3c6b550a943aaab1d692 100644 (file)
--- a/src/soc/fu/regspec.py
+++ b/src/soc/fu/regspec.py
@@ -19,6 +19,7 @@ which MultiCompUnit port, how wide the connection is, and so on.
 
 
 def get_regspec_bitwidth(regspec, srcdest, idx):
+    print ("get_regspec_bitwidth", regspec, srcdest, idx)
     bitspec = regspec[srcdest][idx]
     wid = 0
     print (bitspec)
@@ -67,13 +68,13 @@ class RegSpecALUAPI:
     def get_out(self, i):
         if isinstance(self.rwid, int): # old - testing - API (rwid is int)
             return self.alu.out[i]
-        # regspec-based API: look up variable through regspec according to row number
+        # regspec-based API: look up variable through regspec thru row number
         return getattr(self.alu.n.data_o, self.rwid[1][i][1])
 
     def get_in(self, i):
         if isinstance(self.rwid, int): # old - testing - API (rwid is int)
             return self.alu.i[i]
-        # regspec-based API: look up variable through regspec according to row number
+        # regspec-based API: look up variable through regspec thru row number
         return getattr(self.alu.p.data_i, self.rwid[0][i][1])
 
     def get_op(self):