comment out rlwinm. for now

[soc.git] / src / soc / fu / shift_rot / input_stage.py

diff --git a/src/soc/fu/shift_rot/input_stage.py b/src/soc/fu/shift_rot/input_stage.py
index 72e4c9257540e33abf92c55fedfd6ae734cf3781..f195b40e82e3a1294662ea739f61b5651ade3f06 100644 (file)
--- a/src/soc/fu/shift_rot/input_stage.py
+++ b/src/soc/fu/shift_rot/input_stage.py
@@ -2,15 +2,11 @@
 # the acutal ALU. Things like handling inverting the input, carry_in
 # generation for subtraction, and handling of immediates should happen
 # here
-from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed,
-                    unsigned)
-from nmutil.pipemodbase import PipeModBase
-from soc.decoder.power_enums import InternalOp
-from soc.shift_rot.pipe_data import ShiftRotInputData
-from soc.decoder.power_enums import CryIn
+from soc.fu.common_input_stage import CommonInputStage
+from soc.fu.shift_rot.pipe_data import ShiftRotInputData
 
 
-class ShiftRotInputStage(PipeModBase):
+class ShiftRotInputStage(CommonInputStage):
     def __init__(self, pspec):
         super().__init__(pspec, "input")
 
@@ -21,38 +17,11 @@ class ShiftRotInputStage(PipeModBase):
         return ShiftRotInputData(self.pspec)
 
     def elaborate(self, platform):
-        m = Module()
+        m = super().elaborate(platform) # handles A, carry and sticky overflow
         comb = m.d.comb
 
-        ##### operand A #####
-
-        # operand a to be as-is or inverted
-        a = Signal.like(self.i.ra)
-
-        with m.If(self.i.ctx.op.invert_a):
-            comb += a.eq(~self.i.ra)
-        with m.Else():
-            comb += a.eq(self.i.ra)
-
-        comb += self.o.ra.eq(a)
+        # operands ra and rb
         comb += self.o.rb.eq(self.i.rb)
         comb += self.o.rs.eq(self.i.rs)
 
-
-        ##### carry-in #####
-
-        # either copy incoming carry or set to 1/0 as defined by op
-        with m.Switch(self.i.ctx.op.input_carry):
-            with m.Case(CryIn.ZERO):
-                comb += self.o.carry_in.eq(0)
-            with m.Case(CryIn.ONE):
-                comb += self.o.carry_in.eq(1)
-            with m.Case(CryIn.CA):
-                comb += self.o.carry_in.eq(self.i.carry_in)
-
-        ##### sticky overflow and context (both pass-through) #####
-
-        comb += self.o.so.eq(self.i.so)
-        comb += self.o.ctx.eq(self.i.ctx)
-
         return m